RL56CSMV/3 Conexant Systems, Inc., RL56CSMV/3 Datasheet - Page 5

• Manufacturer Part Number: RL56CSMV/3
• Manufacturer: Conexant Systems, Inc.

Specifications of RL56CSMV/3

• Case: BGA
• Date_code: 9931

RL56CSMV/3 and RL56CSM/3 Hardware Interface Description
List of Figures
Figure 1-1. System Implementation Example Block Diagram .................................................................................................. 1-4
Figure 3-1. RL56CSMV/3 Hardware Interface Signals ............................................................................................................. 3-2
Figure 3-2. RL56CSMV/3 340-Pin BGA Package .................................................................................................................... 3-3
Figure 3-3. Multi Die Ball Grid Array Package........................................................................................................................ 3-17
Figure 3-4. Package Internal Heat Removal Path .................................................................................................................. 3-17
Figure 3-5. Connecting BGA Thermal Balls to Motherboard Ground Plane by Using Thermal Vias...................................... 3-17
Figure 3-6. Test Performance Structure ................................................................................................................................. 3-18
Figure 3-7. SDRAM Interface Timing ..................................................................................................................................... 3-19
Figure 3-8. TDM Bus Timing Diagram .................................................................................................................................... 3-20
Figure 3-9. Oscillator Waveform Requirements ..................................................................................................................... 3-21
Figure 3-10. 16-Mbit SDRAM Interface Connections ............................................................................................................. 3-22
Figure 3-11. 64-Mbit SDRAM Interface Connections ............................................................................................................. 3-23
Figure 4-1. Host Interface Block Diagram ................................................................................................................................ 4-1
Figure 4-2. Reference Direction For Modem Data ................................................................................................................... 4-3
Figure 4-3. Waveforms - Host Read......................................................................................................................................... 4-7
Figure 4-4. Waveforms - Host Write ......................................................................................................................................... 4-8
Figure 4-5. Host DMA Demand Mode Read, DMAMODE = 1 .................................................................................................. 4-9
Figure 4-6. Host DMA Demand Mode Write, DMAMODE = 1 ................................................................................................ 4-10
Figure 5-1. Package Dimensions - 340-Pin BGA ..................................................................................................................... 5-7
Figure 5-2. Plated Hole Placement Guideline for Connection to BGA Ball .............................................................................. 5-8
List of Tables
Table 1-1. RL56CSMV/3 and RL56CSM/3 Models and Functions........................................................................................... 1-1
Table 1-2. Logical Channel vs. Physical Channel .................................................................................................................... 1-4
Table 1-3. Typical SDRAMs ..................................................................................................................................................... 1-5
Table 3-1. RL56CSMV/3 Pin Signals by Pin Location.............................................................................................................. 3-4
Table 3-2. RL56CSMV/3 Pin Signals by Interface.................................................................................................................... 3-6
Table 3-3. RL56CSMV/3 Signal Definitions.............................................................................................................................. 3-8
Table 3-4. I/O Type Descriptions............................................................................................................................................ 3-13
Table 3-5. Digital Electrical Characteristics ............................................................................................................................ 3-14
Table 3-6. Operating Conditions............................................................................................................................................. 3-15
Table 3-7. Absolute Maximum Ratings................................................................................................................................... 3-15
Table 3-8. Current and Power Requirements ......................................................................................................................... 3-16
Table 3-9. Thermal Characteristics ........................................................................................................................................ 3-16
Table 3-10. SDRAM Interface Timing..................................................................................................................................... 3-19
Table 3-11. Timing – T1/E1 Transceiver ................................................................................................................................ 3-20
Table 4-1. Host Control, Status and I/O Registers ................................................................................................................... 4-2
Table 4-2. Timing - Host Read ................................................................................................................................................. 4-7
Table 4-3. Timing - Host Write.................................................................................................................................................. 4-8
Table 4-4. Host Bus Interface Pin Description........................................................................................................................ 4-11
Table 5-1. Clock Oscillator Specifications - Surface Mount...................................................................................................... 5-4
Table 5-2. Clock Oscillator Specifications - Through Hole ....................................................................................................... 5-5
Conexant
1137
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