MT46V16M16P-5B IT Micron Semiconductor Products, MT46V16M16P-5B IT Datasheet
![no-image](/images/no-image-200.jpg)
MT46V16M16P-5B IT
Manufacturer Part Number
MT46V16M16P-5B IT
Description
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46V16M16TG-75Z-IT.pdf
(93 pages)
- Current page: 1 of 93
- Download datasheet (4Mb)
Double Data Rate (DDR) SDRAM
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
Features
• V
• V
• Bidirectional data strobe (DQS) transmitted/
• Internal, pipelined double-data-rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh and self refresh modes
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2-compatible)
• Concurrent auto precharge option supported
•
PDF: 09005aef80768abb/Source: 09005aef80768abb
256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. N, Core DDR: Rev. B 5/08 EN
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
architecture; two data accesses per clock cycle
aligned with data for WRITEs
(x16 has two – one per byte)
t
RAS lockout supported (
DD
DD
= +2.5V ±0.2V, V
= +2.6V ±0.1V, V
Products and specifications discussed herein are subject to change by Micron without notice.
DD
DD
Q = +2.5V ±0.2V
Q = +2.6V ±0.1V (DDR400)
t
RAP =
t
RCD)
1
Notes: 1. Only available on Revision F and G.
Options
• Configuration
• Plastic package – OCPL
• Plastic package
• Timing – cycle time
• Self refresh
• Temperature rating
• Revision
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
– 66-pin TSOP
– 66-pin TSOP (Pb-free)
– 60-ball FBGA (8mm x 14mm)
– 60-ball FBGA (8mm x 14mm) (Pb-free)
– 60-ball FBGA (8mm x 12.5mm)
– 60-ball FBGA (8mm x 12.5mm)
– 5ns @ CL = 3 (DDR400B)
– 6ns @ CL = 2.5 (DDR333) FBGA only
– 6ns @ CL = 2.5 (DDR333) TSOP only
– 7.5ns @ CL = 2 (DDR266)
– 7.5ns @ CL = 2 (DDR266A)
– 7.5ns @ CL = 2.5 (DDR266B)
– Standard
– Low-power self refresh
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– x4, x8
– x16
– x4, x8, x16
(Pb-free)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. Only available on Revision K.
3. Not recommended for new designs.
256Mb: x4, x8, x16 DDR SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Marking
Features
16M16
64M4
32M8
-75E
-75Z
None
None
BG
-75
FG
CV
CY
-5B
-6T
TG
:G
:F
IT
-6
:K
P
L
3
3
2
1
1
2
1
1
1
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