GS81302Q09GE-250 GSI Technology, GS81302Q09GE-250 Datasheet

GS81302Q09GE-250

Manufacturer Part Number

GS81302Q09GE-250

Description

BGA 165/Synchronous NBT SRAM

Manufacturer

GSI Technology

Datasheet

1.GS81302Q09GE-250.pdf (34 pages)

Specifications of GS81302Q09GE-250

Pack_quantity

105

Comm_code

85423245

Lead_time

Current page: 1 of 34
Download datasheet (2Mb)

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Supporter

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ Family Overview

The GS81302Q08/0918/36E are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (72Mb)

SRAMs. The GS81302Q08/09/18/36E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302Q08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Rev: 1.00c 4/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tKHKH

tKHQV

Parameter Synopsis

0.45 ns

4.0 ns

-250

1/34

144Mb SigmaQuad-II

Burst of 2 SRAM

Because Separate I/O SigmaQuad-II B2 RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read or

write transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a SigmaQuad-II B2 RAM is always one address pin

less than the advertised index depth (e.g., the 8M x 18 has a

4M addressable index).

0.45 ns

5.0 ns

-200

1 mm Bump Pitch, 11 x 15 Bump Array

6.0 ns

0.5 ns

165-Bump, 15 mm x 17 mm BGA

-167

GS81302Q08/09/18/36E-250/200/167

Bottom View

1.8 V and 1.5 V I/O

250 MHz–167 MHz

Preliminary

1.8 V V

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