GS81302QT37GE-250 GSI Technology, GS81302QT37GE-250 Datasheet
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GS81302QT37GE-250
Manufacturer Part Number
GS81302QT37GE-250
Description
Manufacturer
GSI Technology
Datasheet
1.GS81302QT37GE-250.pdf
(30 pages)
Specifications of GS81302QT37GE-250
Pack_quantity
1
Comm_code
85423245
Lead_time
70
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS81302QT07/10/19/37E are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302QT07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Rev: 1.00 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write (BW), and Clock (K, K) inputs
tKHKH
tKHQV
0.45 ns
3.0 ns
-333
144Mb SigmaQuad-II+
Burst of 2 SRAM
Parameter Synopsis
1/30
0.45 ns
3.3 ns
-300
Clocking and Addressing Schemes
The GS81302QT07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B2 RAMs always
transfer data in two packets, A0 is internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfer. Because the LSB is tied off internally, the
address field of a SigmaQuad-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 8M x
18 has a 4M addressable index).
GS81302QT07/10/19/37E-333/300/250/200
1 mm Bump Pitch, 11 x 15 Bump Array
0.45 ns
4.0 ns
-250
165-Bump, 15 mm x 17 mm BGA
TM
Bottom View
0.45 ns
5.0 ns
-200
© 2011, GSI Technology
1.8 V and 1.5 V I/O
333 MHz–200 MHz
1.8 V V
DD