GS815036AB-250I GSI Technology, GS815036AB-250I Datasheet

GS815036AB-250I

Manufacturer Part Number

GS815036AB-250I

Description

119 BGA/GS815036AB-250I

Manufacturer

GSI Technology

Datasheet

1.GS815036AB-250I.pdf (25 pages)

Specifications of GS815036AB-250I

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 25
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119-Bump BGA

Commercial Temp

Industrial Temp

Features

• Register-Register Late Write mode, Pipelined Read mode

• 2.5 V +200/–200 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• ZQ controlled programmable output drivers

• Dual Cycle Deselect

• Fully coherent read and write pipelines

• Byte write operation (9-bit bytes)

• Differential HSTL clock inputs, K and K

• Asynchronous output enable

• Sleep mode via ZZ

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• JEDEC-standard 119-bump BGA package

• Pb-Free 119-bump BGA package available

Family Overview

GS815018/36A are 18,874,368-bit (18Mb) high performance

SRAMs. This family of wide, low voltage HSTL I/O SRAMs

is designed to operate at the speeds needed to implement

economical high performance cache systems.

Rev: 1.05 10/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

18Mb Register-Register Late Write SRAM

Pipeline

1M x 18, 512K x 36

Curr (x18)

Curr (x36)

tKHQV

Cycle

Parameter Synopsis

1/25

-357

600

650

2.8

1.4

Functional Description

Because GS815018/36A are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

GS815018/36A support pipelined reads utilizing a rising-edge-

triggered output register. They also utilize a Dual Cycle

Deselect (DCD) output deselect protocol.

GS815018/36A are implemented with high performance

technology and are packaged in a 119-bump BGA.

Mode Control

There are two mode control select pins (M1 and M2), which

allow the user to set the correct read protocol for the design.

The GS815018/36A support single clock Pipeline mode, which

directly affects the two mode control select pins. In order for

the part to fuction correctly, and as specified, M1 must be tied

to VSS and M2 must be tied to V

at power-up and should not be changed during operation.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

-333

550

600

3.0

1.5

-300

500

550

3.3

1.6

GS815018/36AB-357/333/300/250

-250

450

500

4.0

2.0

Unit

or V

DDQ

250 MHz–357 MHz

Product Preview

. This must be set

2.5 V V

HSTL I/O

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