GS816118BD-150 GSI Technology, GS816118BD-150 Datasheet
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GS816118BD-150
Manufacturer Part Number
GS816118BD-150
Description
Manufacturer
GSI Technology
Datasheet
1.GS816118BD-150.pdf
(35 pages)
Specifications of GS816118BD-150
Pack_quantity
144
Comm_code
85423245
Lead_time
70
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
• Single Cycle Deselect (SCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard
• RoHS-compliant 100-pin TQFP and 165-bump BGA packages
Functional Description
Applications
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
Rev: 1.04 6/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
operation
BGA packages
available
100-lead TQFP 100-pin TQFP and 165-bump
Flow Through
Pipeline
3-1-1-1
2-1-1-1
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
Curr
Curr
Curr
Curr
tCycle
tCycle
Parameter Synopsis
t
(x32/x36)
t
(x32/x36)
KQ
KQ
(x18)
(x18)
1/35
GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
SCD Pipelined Reads
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is a
SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD
(Dual Cycle Deselect) versions are also available. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and
2.5 V compatible. Separate output power (V
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
-250
295
345
225
255
2.5
4.0
5.5
5.5
-200
245
285
200
220
3.0
5.0
6.5
6.5
-150
200
225
185
205
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2004, GSI Technology
250 MHz–150 MHz
DDQ
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
) pins are used to
DD