GS8320Z36GT-133IV GSI Technology, GS8320Z36GT-133IV Datasheet

GS8320Z36GT-133IV

Manufacturer Part Number

GS8320Z36GT-133IV

Description

Manufacturer

GSI Technology

Datasheet

1.GS8320Z36GT-133IV.pdf (23 pages)

Specifications of GS8320Z36GT-133IV

Pack_quantity

Comm_code

85423245

Lead_time

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8320Z18/36T-xxxV is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.02a 12/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

36Mb Pipelined and Flow Through

Flow

Synchronous NBT SRAMs

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/23

-250 -225 -200 -166 -150 -133 Unit

285

350

205

235

3.0

4.0

6.5

265

320

195

225

3.0

4.4

7.0

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8320Z18/36T-xxxV may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS8320Z18/36T-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

245

295

185

210

3.0

5.0

7.5

220

260

175

200

3.5

6.0

8.0

210

240

165

190

3.8

6.6

8.5

185

215

155

175

4.0

7.5

8.5

GS8320Z18/36T-xxxV

250 MHz–133 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

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