GS8342T36BGD-250 GSI Technology, GS8342T36BGD-250 Datasheet

GS8342T36BGD-250

Manufacturer Part Number

GS8342T36BGD-250

Description

PBGA 165/1M X 36 DDR SRAM, 0.45 ns

Manufacturer

GSI Technology

Datasheet

1.GS8342T36BGD-250.pdf (36 pages)

Specifications of GS8342T36BGD-250

Pack_quantity

Comm_code

85423245

Lead_time

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

GS8342T36BGD-250

Manufacturer:

GSI

Quantity:

20 000

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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18 and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaDDR™ Family Overview

The GS8342T08/09/18/36BD are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342T08/09/18/36BD SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342T08/09/18/36BD SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Rev: 1.00 4/2011

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

devices

tKHKH

tKHQV

0.45 ns

2.5 ns

36Mb SigmaDDR-II

-400

Burst of 2 SRAM

Parameter Synopsis

1/36

2.86 ns

0.45 ns

-350

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaDDR-II B2 RAMs always

transfer data in two packets. When a new address is loaded, A0

presets an internal 1 bit address counter. The counter

increments by 1 (toggles) for each beat of a burst of two data

transfer.

Common I/O x8 and x9 SigmaDDR-II B2 RAMs always

transfer data in two packets. When a new address is loaded,

the LSB is internally set to 0 for the first read or write transfer,

and incremented by 1 for the next transfer. Because the LSB

is tied off internally, the address field of a x8/x9 SigmaDDR-II

B4 RAM is always one address pin less than the advertised

index depth force return (e.g., the 4M x 8 has a 2M addressable

index).

0.45 ns

3.0 ns

-333

GS8342T08/09/18/36BD-400/350/333/300/250

1 mm Bump Pitch, 11 x 15 Bump Array

0.45 ns

3.3 ns

-300

165-Bump, 13 mm x 15 mm BGA

0.45 ns

4.0 ns

Bottom View

-250

1.8 V and 1.5 V I/O

400 MHz–250 MHz

Preliminary

1.8 V V

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