GS8640FZ36T-7.5I GSI Technology, GS8640FZ36T-7.5I Datasheet

GS8640FZ36T-7.5I

Manufacturer Part Number

GS8640FZ36T-7.5I

Description

TQFP 100

Manufacturer

GSI Technology

Datasheet

1.GS8640FZ18GT-6.5I.pdf (21 pages)

Specifications of GS8640FZ36T-7.5I

Pack_quantity

Comm_code

85423245

Lead_time

994

Current page: 1 of 21
Download datasheet (474Kb)

Packages listed with the additional “G” designator are 6/6 RoHS compliant.

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8640FZ18/36T is a 72Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other flow

through read/single late write SRAMs, allow utilization of all

Rev: 1.00b 2/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

Flow Through NtRAM™, NoBL™ and ZBT™ SRAMs

Through

2-1-1-1

Flow

Synchronous NBT SRAM

Curr

72Mb Flow Through

tCycle

(x18)

(x36)

Parameter Synopsis

1/21

-5.5

285

330

5.5

available bus bandwidth by eliminating the need to insert

deselect cycles when the device is switched from read to write

cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8640FZ18/36T is configured to operate in Flow

Through mode.

The GS8640FZ18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

-6.5

245

280

6.5

-7.5

220

250

7.5

210

240

8.0

-8

GS8640FZ18/36T-5.5/6.5/7.5/8

Unit

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

5.5 ns–8 ns

Related parts for GS8640FZ36T-7.5I

Related keywords

GS8640FZ36T-7.5I datasheet
GS8640FZ36T-7.5I data sheet
GS8640FZ36T-7.5I pdf datasheet
GS8640FZ36T-7.5I component
GS8640FZ36T-7.5I part
GS8640FZ36T-7.5I distributor
GS8640FZ36T-7.5I RoHS
GS8640FZ36T-7.5I datasheet download