GS8640Z36GT-300 GSI Technology, GS8640Z36GT-300 Datasheet

GS8640Z36GT-300

Manufacturer Part Number

GS8640Z36GT-300

Description

100 TQFP

Manufacturer

GSI Technology

Datasheet

1.GS8640Z18GT-167.pdf (24 pages)

Specifications of GS8640Z36GT-300

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 24
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Packages listed with the additional “G” designator are 6/6 RoHS compliant.

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.03a 10/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/24

-300

400

480

285

330

2.3

3.3

5.5

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8640Z18/36T may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, meaning that in addition to the rising edge

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8640Z18/36T is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

-250

340

410

245

280

2.5

4.0

6.5

-200

290

350

220

250

3.0

5.0

7.5

GS8640Z18/36T-300/250/200/167

-167

260

305

210

240

3.4

6.0

8.0

Unit

300 MHz–167 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

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