GS880F36CGT-6.5I GSI Technology, GS880F36CGT-6.5I Datasheet

GS880F36CGT-6.5I

Manufacturer Part Number

GS880F36CGT-6.5I

Description

TQFP 100

Manufacturer

GSI Technology

Datasheet

1.GS880F36CGT-6.5I.pdf (23 pages)

Specifications of GS880F36CGT-6.5I

Pack_quantity

Comm_code

85423245

Lead_time

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• Flow Through mode operation; Pin 14 = No Connect

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS880F18/32/36CT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.00 9/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

2-1-1-1

512K x 18, 256K x 32, 256K x 36

Curr (x32/x36)

Curr (x18)

tCycle

9Mb Sync Burst SRAMs

Paramter Synopsis

1/23

-4.5

TBD

4.5

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Designing For Compatibility

The JEDEC standard for Burst RAMS calls for a FT mode pin

option on Pin 14. Board sites for flow through Burst RAMS

should be designed with V

to ensure the broadest access to multiple vendor sources.

Boards designed with FT pin pads tied low may be stuffed with

GSI’s pipeline/flow through-configurable Burst RAMs or any

vendor’s flow through or configurable Burst SRAM. Boards

designed with the FT pin location tied high or floating must

employ a non-configurable flow through Burst RAM, like this

RAM, to achieve flow through functionality.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS880F18/32/36CT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

TBD

5.0

-5

-5.5

TBD

5.5

GS880F18/32/36CT-4.5/5/5.5/6.5/7.5

DDQ

-6.5

TBD

6.5

) pins are used to decouple output noise

-7.5

TBD

7.5

connected to the FT pin location

Unit

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

4.5 ns–7.5 ns

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