R5F562TAADFP Renesas Electronics Corporation., R5F562TAADFP Datasheet

R5F562TAADFP

Manufacturer Part Number

R5F562TAADFP

Description

Manufacturer

Renesas Electronics Corporation.

Datasheets

1.R5F562TAADFH.pdf (94 pages)

2.R5F562TAADFP.pdf (94 pages)

3.R5F562TAADFP.pdf (94 pages)

Specifications of R5F562TAADFP

Pack_quantity

Comm_code

85423990

Lead_time

126

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Amily Shenzhen XNWY Technology Co., Ltd

Part Number:

R5F562TAADFP

Company:

Amily Shenzhen XNWY Technology Co., Ltd

Part Number:

R5F562TAADFP#11

Company:

BOSTOCK HK LIMITED

Part Number:

R5F562TAADFP#V0

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

R5F562TAADFP#V1

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

R5F562TAADFP#V1

Manufacturer:

RENESAS/瑞萨

Quantity:

20 000

Current page: 1 of 94
Download datasheet (635Kb)

RX62T Group

Renesas MCUs

100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data

capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary

channels and four single-phase complementary channels or three three-phase

complementary channels and one single-phase complementary channel)

R01DS0096EJ0100 Rev.1.00

Apr 20, 2011

Features

■ 32-bit RX CPU core

■ Operating voltage

■ Low-power design and architecture

■ On-chip main flash memory, no wait states

■ On-chip data flash memory

■ On-chip SRAM, no wait states

■ DMA

■ Reset and supply management

■ Clock functions

■ Independent watchdog timer

 Max. operating frequency: 100 MHz

 Single precision 32-bit IEEE-754 floating point

 Accumulator handles 64-bit results (for a single

 Multiplication and division unit handles 32- × 32-bit

 Fast interrupt

 Divider (fastest instruction execution takes two CPU

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Background JTAG debugging plus high-speed tracing

 Single 3.3- or 5-V supply; 5-V analog supply is possible

 Four low-power modes

 100-MHz operation, 10-ns read cycle

 No wait states for reading at full CPU speed

 64-Kbyte/128-Kbyte/256-Kbyte capacities

 For instructions and operands

 User code programmable via the SCI or JTAG

 Max. 32 Kbytes, reprogrammable up to 30,000 times

 Erasing and programming impose no load on the CPU.

 8-Kbyte/16-Kbyte SRAM

 For instructions and operands

 DTC: The single unit is capable of transfer on multiple

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

 External crystal oscillator or internal PLL for operation at

 Internal 125-kHz LOCO for the IWDT

 Detection of main oscillator stoppage (for IEC 60730

 125-kHz LOCO clock operation

 Software is incapable of stopping the robust WDT.

(for IEC60730compliance)

Capable of 165 DMIPS in operation at 100 MHz

instruction) from 32- × 32-bit operations

operations (multiplication instructions take one CPU

clock cycle)

clock cycles)

with 3.3-V products

channels

8 to 12.5 MHz

compliance)

■ Up to 7 communications interfaces

■ Up to 16 16-bit timers

■ Three A/D converter units for 1-MHz operation,

■ CRC (cyclic redundancy check) calculation unit

■ Up to 61 input–output ports and up to 21 input-only

■ Operating temp. range

 1: CAN (compliant with ISO11898-1), incorporating 32

 3: SCIs, with asynchronous mode (incorporating noise

 1: I2C bus interface, capable of SMBus operation

 1: RSPI

 1: LIN

 8: 16-bit MTU3: 100-MHz operation, input capture,

 4: 16-bit GPT: 100-MHz operation, input capture, output

 4: 16-bit CMT

 Three units are capable of simultaneous sampling on

 Self diagnosis (for IEC60730 compliance)

 8: Two 12-bit ADC units: three sample-and-hold circuits,

 12: Single 10-bit ADC unit

 Monitoring of data being transferred (for IEC 60730

 Monitoring of data in memory (for IEC 60730

 PORT registers: Monitoring of output ports (for IEC

 –40C to +85C

for a total of 20 channels

ports

mailboxes

cancellation), clock-synchronous mode, and smart-card

interface mode

output compare, two three-phase complementary PWM

output channels, complementary PWM imposing no load

on the CPU, phase-counting mode

compare, four complementary single-phase PWM output

channels, or one three-phase complementary PWM

output channel and one single-phase complementary

PWM output channel, complementary PWM imposing no

load on the CPU, operation linked with comparator (for

counting and control of PWM-signal negation), detection

of abnormal oscillation frequencies (for IEC 60730

compliance)

seven channels

double data registers, amplifier, comparator

compliance)

60730 compliance)

PLQP0112JA-A 20×20mm, 0.65mm pitch

PLQP0100KB-A 14×14mm, 0.5mm pitch

PLQP0080JA-A 14×14mm, 0.65mm pitch

PLQP0064KB-A 10×10mm, 0.5mm pitch

Datasheet

R01DS0096EJ0100

Page 1 of 92

Apr 20, 2011

Rev.1.00

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