74F194PC Fairchild Semiconductor, 74F194PC Datasheet - Page 2

• Manufacturer Part Number: 74F194PC
• Description: IC REGISTER BIDIRECT 4BIT 16-DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F194PC

• Logic Type: Register, Bidirectional
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Function: Universal
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F194

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Unit Loading/Fan Out
Functional Description
The 74F194 contains four edge-triggered D-type flip-flops
and the necessary interstage logic to synchronously per-
form shift right, shift left, parallel load and hold operations.
Signals applied to the Select (S
type of operation, as shown in the Mode Select Table. Sig-
nals on the Select, Parallel data (P
(D
state, provided only that the recommended setup and hold
times, with respect to the clock rising edge, are observed.
A LOW signal on Master Reset (MR) overrides all other
inputs and forces the outputs LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
SR
, D
SL
) inputs can change when the clock is in either
S
P
D
D
CP
MR
Q
0
0
Pin Names
SR
SL
0
, S
–P
–Q
1
3
3
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
0
, S
1
0
) inputs determine the
–P
3
) and Serial data
Description
2
Mode Select Table
H (h)
L (l)
p
output) one setup time prior to the LOW-to-HIGH clock transition.
X
Reset
Hold
Shift Left
Shift Right
Parallel Load H
n
Operating
(q
Immaterial
n
Mode
)
LOW Voltage Level
HIGH Voltage Level
Lower case letters indicate the state of the referenced input (or
MR S
H
H
H
H
H
L
HIGH/LOW
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
X
h
h
h
l
l
l
U.L.
1
S
X
h
h
h
Inputs
l
l
l
0
D
X
X
X
X
X
h
SR
l
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
D
Input I
1 mA/20 mA
X
X
X
X
X
h
SL
l
P
p
X
X q
X q
X q
X
X
n
n
IH
OH
/I
Q
p
H q
/I
L
L
IL
0
1
1
0
0
OL
Outputs
Q
q
q
q
q
p
L
1
2
2
0
0
1
1
Q
q
q
q
q
q
p
L
2
3
3
1
1
2
2
Q
q
q
q
p
H
L
L
3
2
2
3
3