74F299SC Fairchild Semiconductor, 74F299SC Datasheet - Page 2

• Manufacturer Part Number: 74F299SC
• Description: IC REGIST SHIFT/STOR OCT 20-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F299SC

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Universal
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Unit Loading/Fan Out
Functional Description
The 74F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S
the Mode Select Table. All flip-flop outputs are brought out
through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE outputs are also disabled by
HIGH signals on both S
lel load operation.
Mode Select Table
H
L

X
LOW Voltage Level
MR S
HIGH Voltage Level
Immaterial
H
H
H
H
L
LOW-to-HIGH Clock Transition
CP
DS
DS
S
MR
OE
I/O
Q
Inputs
Pin Names
0
0
X
H H
H
L
L
, S
, Q
1
0
0
7
1
–I/O
, OE
S
1
X
H
7
L
L
0
7
2
CP



X Asynchronous Reset; Q
X Hold
Parallel Load; I/O
Shift Right; DS
Shift Left; DS
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
3-STATE Parallel Outputs
Serial Outputs
0
and S
1
or OE
1
in preparation for a paral-
Response
7
0
2
0
disables the 3-STATE
n
Q
and S
Q
7
Description
, Q
0
Q
, Q
7
n
0
1
–Q
, as shown in
0
7
Q
0
Q
6
, etc.
and Q
1
LOW
, etc.
7
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
150/40(33.3)
HIGH/LOW
3.5/1.083
50/33.3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
U.L.
3 mA/24 mA (20 mA)
70 A/ 0.65 mA
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 1.2 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
Input I
1 mA/20 mA
IH
OH
/I
/I
IL
OL