HDSP-5301 Agilent(Hewlett-Packard), HDSP-5301 Datasheet

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HDSP-5301

Manufacturer Part Number
HDSP-5301
Description
14.2 mm (0.56 inch) Seven Segment Displays
Manufacturer
Agilent(Hewlett-Packard)
Datasheet
(5/97)
Gigabit Ethernet Transceiver Chip
Preliminary Technical Data
Features
• IEEE 802.3z Gbit Ethernet
• Based on X3T11 “10 Bit
• Low Power Consumption
• Transmitter and Receiver
• Two Package Sizes
• 10-Bit Wide Parallel TTL
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 KV ESD Protection
Applications
• 1250 MBd Gigabit Ethernet
• High Speed Proprietary
• Backplane Serialization
• Bus Extender
Description
The HDMP-1636/46 transceiver is
a single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
Compatible, Supports 1250
MBd Gigabit Ethernet
Specification”
Functions Incorporated onto
a Single IC
Available:
– 10 mm PQFP (HDMP-1636)
– 14 mm PQFP (HDMP-1646)
Compatible I/Os
Interface
Interface
provides complete Serialize/
Deserialize for copper transmis-
sion, incorporating both the
Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is
then multiplied by 10, to gener-
ate the 1250 MHz serial signal
clock used to generate the high
speed output. The high speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber optic module for
optical transmission.
HDMP-1636 Transceiver
HDMP-1646 Transceiver
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality, controlled
through an external input pin.
Additionally, the byte
711

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HDSP-5301 Summary of contents

Page 1

Gigabit Ethernet Transceiver Chip Preliminary Technical Data Features • IEEE 802.3z Gbit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption • Transmitter and Receiver Functions Incorporated onto a Single IC ...

Page 2

PROTOCOL DEVICE BYTSYNC REFCLK ENBYTSYNC Figure 1. Typical Application Using the HDMP-16x6. DATA BYTE FRAME TX[0-9] TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR REFCLK RXCAP0 RXCAP1 RBC0 RBC1 FRAME DATA BYTE DEMUX RX[0-9] BYTE SYNC BYTSYNC Figure 2. HDMP-16x6 Transceiver Block Diagram. ...

Page 3

This may be useful in proprietary applications which use alternative methods to align the parallel data. HDMP-1636/46 Block Diagram The HDMP-1636/46 was designed to transmit and receive 10-bit wide parallel data over a single high-speed ...

Page 4

These clocks are 180 degrees out of phase with each other, and are alternately used to clock the 10-bit parallel output data. INPUT SAMPLER The INPUT SAMPLER is respon- sible for converting the serial input signal ...

Page 5

REFCLK TX[0]-TX[9] DATA t SETUP Figure 3. Transmitter Section Timing.    ± DOUT TX[0]-TX[9] REFCLK Figure 4. Transmitter Latency ...

Page 6

HDMP-1636/46 (Receiver Section) Timing Characteristics + 3. 3. Symbol [1,2] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data ...

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HDMP-1636/46 (TRx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent A damage to this device. Symbol V Supply Voltage CC V TTL Input Voltage IN,TTL ...

Page 8

HDMP-1636/46 (TRx) AC Electrical Specifications + 3. 3. Symbol t Input TTL Rise Time, 0.8 to 2.0 Volts r,TTLin t Input TTL Fall Time, 2.0 to 0.8 ...

Page 9

HDMP-1636/46 (Transmitter Section) Output Jitter Characteristics + 3. 3. Symbol [1] RJ Random Jitter at DOUT, the High Speed Electrical Data Port, specified as 1 sigma deviation ...

Page 10

I/O Type Definitions I/O Type I-TTL Input TTL, Floats High When Left Open O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground HDMP-1636/46 (TRx) Pin Input Capacitance ...

Page 11

GND_TXTTL 2 TX[0] TX[1] 3 TX[ _TXTTL TX[3] TX[4] 7 TX[ TX[6] xxxx-x Rz.zz V _TXTTL ...

Page 12

TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL -DIN 52 HS_IN +DIN 54 -DOUT 61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when +DOUT 62 ENBYTSYNC 24 I-TTL GND GND_RXA 51 S ...

Page 13

TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL RX[1] 44 RX[2] 43 RX[3] 41 RX[4] 40 RX[5] 39 RX[6] 38 RX[7] 36 RX[8] 35 RX[9] 34 RXCAP0 48 C RXCAP1 49 TX[0] 2 I-TTL TX[1] 3 TX[2] 4 ...

Page 14

V CC GND_TXTTL V _TXTTL CC TOP VIEW V _TXTTL CC GND_TXTTL GND_TXA TXCAP1 C PLLT SUPPLY VOLTAGE INTO V BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF. ...

Page 15

Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity Mechanical Dimensions PIN # ...

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