AK4640_05 AKM [Asahi Kasei Microsystems], AK4640_05 Datasheet - Page 16
AK4640_05
Manufacturer Part Number
AK4640_05
Description
16-Bit ?? CODEC with MIC/HP/SPK-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4640_05.pdf
(78 pages)
- Current page: 16 of 78
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ASAHI KASEI
Parameter
Control Interface Timing (4-wire Serial mode):
Control Interface Timing (I
Reset Timing
Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 28. The AK4640 can be reset by the PDN pin = “L”.
Note 29. This is the count of LRCK “↑” from the PMADC bit = “1”.
MS0273-E-02
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
PDN Pulse Width
PMADC “↑” to SDTO valid
Pulse Width High
2
C Bus mode):
(Note 29)
(Note 27)
(Note 28)
- 16 -
tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
Symbol
tCCKH
tCCKL
tHIGH
tLOW
tCSW
tCCK
tCDH
tDCD
tCDS
tCSH
tCCZ
tBUF
tPDV
tCSS
fSCL
tPD
tSP
tR
tF
0.25
min
200
150
150
4.7
4.0
4.7
4.0
4.7
4.0
80
80
40
40
50
50
0
0
-
-
-
-
-
-
2081
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
100
0.3
1.0
50
70
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[AK4640]
2005/04
Units
kHz
1/fs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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