ISPGDXTMFAMILY LATTICE [Lattice Semiconductor], ISPGDXTMFAMILY Datasheet - Page 13

• Manufacturer Part Number: ISPGDXTMFAMILY
• Description: In-System Programmable Generic Digital CrosspointTM
• Manufacturer: LATTICE [Lattice Semiconductor]

Third-Party Timing Simulation
The ispGDX Design System will generate simulation
netlists as specified by a user. The simulation netlist
formats available are: EDIF, Verilog (OVI compliant),
VHDL (VITAL compliant), Viewlogic, and OrCAD.
All necessary programming of the ispGDX Family is done
via five TTL level logic interface signals. These five
signals are fed into the on-chip programming circuitry
where a state machine controls the programming.
On-chip programming can be accomplished using either
an IEEE 1149.1 boundary scan protocol or a Lattice
industry-standard ISP programming protocol. The IEEE
1149.1-compliant interface signals are Test Data In (TDI),
Test Data Out (TDO), Test Clock (TCK) and Test Mode
Table 2. Operating Mode Control Signals
Figure 5. ISP Device Programming Interface
SDO
In-System Programmability
BSCAN/ispEN
SDI
Download
.jed - JEDEC Device Programming File
MODE
SCLK
ispEN
0
1
BSCAN/ispEN
ispGDX
80A
5-wire
Programming
Interface
Program Device Using Lattice ISP Protocol
Program Device or Normal Operation Using IEEE 1149.1 Protocol
BSCAN/ispEN
ispGDX
120A
BSCAN/ispEN
ispGDX
OPERATION
160/A
13
Specifications ispGDX Family
For In-System Programming, Lattice’s ispGDX devices
may be programmed, alone or in a chain with up to 100
other Lattice ISP devices, using Lattice’s ISP Daisy
Chain Download software.
based tool can be launched from the Tool Bar or by
Invoking the Download option from the drop down menu
within the ispGDX Design System. ISP Daisy Chain
Download version 5.0 or above supports the ispGDX
Family devices.
Select (TMS) control. The corresponding Lattice ISP
control signals are SDI, SDO, SCLK and MODE. These
signals switch their operation from IEEE 1149.1 bound-
ary scan protocol to Lattice ISP programming protocol
based on the state of the BSCAN/ispEN pin as shown in
Table 2. Figure 5 illustrates the block diagram for the ISP
programming interface. Figure 6 illustrates the block
diagram for the ispJTAG interface.
Figure 6. ispJTAG Device Programming Interface
TDO
TDI
TMS
TCK
BSCAN/ispEN
ispGDX
80A
ispJTAG
Programming
Interface
BSCAN/ispEN
ispGDX
CONTROL PIN FUNCTION
120A
SDI, SDO, SCLK, MODE
TDI, TDO, TCK, TMS
This powerful Windows-
VCC
Op Mode Signals/ispGDX
BSCAN/ispEN
ispGDX
160/A