73K302L TDK [TDK Electronics], 73K302L Datasheet
73K302L
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73K302L Summary of contents
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... Bell 202, 212A and 103 compatible modem. The 73K302L is an enhancement of the 73K212L single-chip modem with Bell 202 mode features added. The 73K302L is capable of 1200 or 0-300 bit/s full-duplex operation over dial-up lines. 4-wire full-duplex capability and a low speed back channel are also provided in Bell 202 mode. The ...
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... An ALE control line simplifies address demultiplexing. Data occurs through a separate serial port only. The 73K302L is ideal for use in either free standing or integral system modem products where multi- standard data communications is desired. Its high functionality, low power consumption and efficient packaging ...
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... SERIAL COMMAND INTERFACE MODE The serial command interface allows access to the 73K302L control and status registers via a serial command port. In this mode the AD0, AD1 and AD2 a frequency lines provide register addresses for data passed through the data pin under control of the RD and WR lines ...
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... INT will stay low until the processor reads the detect register or does a full reset. I Read. A low requests a read of the 73K302L internal registers. Data cannot be output unless both RD and the latched CS are active or low. I Reset. An active high signal on this pin will put the chip into an inactive state ...
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... Read data is provided LSB first. Data will not be output unless the RD signal is active. I Write. A low on this input informs the 73K302L that data or status information has been shifted in through the DATA pin and is available for writing to an internal register. The normal procedure for a write is to shift in data LSB first on the DATA pin for eight consecutive falling edges of EXCLK and then to pulse WR low ...
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Bell 212A, 103, 202 Single-Chip Modem PIN DESCRIPTION (continued) DTE USER INTERFACE NAME PLCC/PIN DIP NUMBER EXCLK 19 RXCLK 23 RXD 22 TXCLK 18 TXD 21 ANALOG INTERFACE AND OSCILLATOR RXA 27 TXA 16 XTL1 2 XTL2 3 TYPE DESCRIPTION ...
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... NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as 0' Undefined, mask in software. microprocessor and the 73K302L internal state detect register which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and RXD output gate used in the modem initial connect sequence ...
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Bell 212A, 103, 202 Single-Chip Modem REGISTER ADDRESS TABLE ADDRESS REGISTER AD2 - AD0 D7 CONTROL MODULATION REGISTER CR0 000 OPTION 0 0=103 FSK 1=202 FSK TRANSMIT CONTROL CR1 001 PATTERN REGISTER 1 1 00=TX DATA 01=TX ALTERNATE 10=TX MARK ...
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CONTROL REGISTER CR0 MODUL. 0 000 OPTION BIT NO. NAME D0 Answer/ Originate D1 Transmit Enable D5, D4,D3, D2 Transmit Mode TRANSMIT TRANSMIT TRANSMIT MODE 3 MODE 2 MODE 1 CONDITION DESCRIPTION 0 Selects ...
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Bell 212A, 103, 202 Single-Chip Modem CONTROL REGISTER 0 (continued CR0 MODUL. 0 000 OPTION BIT NO. NAME D6 D7 Modulation Option CONTROL REGISTER CR1 TRANSMIT TRANSMIT 001 PATTERN PATTERN 1 0 BIT NO. NAME ...
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CONTROL REGISTER 1 (continued CR1 TRANSMIT TRANSMIT 001 PATTERN PATTERN 1 0 BIT NO. NAME D3 CLK Control D4* Bypass Scrambler/ Add Phase Equalization D5 Enable Detect D7, D6 Transmit Pattern * D4 should always be set to ...
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Bell 212A, 103, 202 Single-Chip Modem DETECT REGISTER 010 BIT NO. NAME D0 Long Loop D1 Call Progress Detect D2 Special Tone Detect D3 Carrier Detect D4 Unscrambled Mark Detect D5 Receive Data D6, D7 ...
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TONE REGISTER RXD TRANSMIT 011 OUTPUT SOFT CONTR. CARRIER TURN-OFF TONE BIT NO. NAME D0 DTMF 0/ Special Tone Detect/Select D1 DTMF 1/ Overspeed D2 DTMF2/202T FDX D3, D2, D1, D0 DTMF ...
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... Notes for Tone Register use detect SCT tone, 202 answer mode must be selected. 2. For answer tone detection, 103 or 212 originate mode must be active. To transmit answer tone, the 73K302L must be in 103 or 212 answer mode. 3. After completion of DTMF dialing, bit D2 should be reset unless 202 full-duplex mode is selected. ...
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... D7, D6, D5, D4 Device Identification Signature D3-D0 Not Used CONDITION DESCRIPTION Indicates Device 73K212AL, 73K321L or 73K322L 73K221AL or 73K302L 73K222AL , 73K222BL 73K224L 73K324L 73K224BL 73K324B L ...
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Bell 212A, 103, 202 Single-Chip Modem ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and ...
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DC ELECTRICAL CHARACTERISTICS (TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.) PARAMETER IDD, Supply Current IDDA, Active IDD1, Power-down IDD2, Power-down Digital Inputs VIH, Input High Voltage Reset, XTL1, XTL2 All other inputs VIL, Input Low ...
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Bell 212A, 103, 202 Single-Chip Modem ELECTRICAL SPECIFICATIONS DYNAMIC CHARACTERISTICS AND TIMING (TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.) PARAMETER DPSK Modulator Carrier Suppression Output Amplitude FSK Modulator Output Freq. Error Transmit Level Soft Carrier ...
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DYNAMIC CHARACTERISTICS AND TIMING PARAMETER Call Progress Detector Detect Level Reject Level Delay Time Hold Time Hysteresis Carrier Detect Threshold Delay Time Bell 103 Bell 212A Bell 202 Forward Channel Bell 202 Back Channel Hold Time Bell 103 Bell 212A ...
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Bell 212A, 103, 202 Single-Chip Modem DYNAMIC CHARACTERISTICS AND TIMING PARAMETER Special Tone Detectors (continued) Hold Time Answer tone 900 Hz SCT tone 202 Main Channel Mark 202 Back Channel Mark 1270 or 2225 Hz marks Hysteresis Detect Freq. Range ...
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DYNAMIC CHARACTERISTICS AND TIMING PARALLEL CONTROL INTERFACE PARAMETER Timing (Refer to Timing Diagrams) TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD TWW TRD TRDF TCKD TCKW TDCK TAC TCA TWH Control for setup is the falling edge ...
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Bell 212A, 103, 202 Single-Chip Modem TIMING DIAGRAMS BUS TIMING DIAGRAM (PARALLEL VERSION) TLL ALE RD WR TAL AD0-AD7 ADDRESS CS READ TIMING DIAGRAM (SERIAL MODE EXCLK TRCLK RD TAR TRA ADDRESS A0-A2 TRD D0 DATA WRITE TIMING ...
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APPLICATIONS INFORMATION GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line ...
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Bell 212A, 103, 202 Single-Chip Modem APPLICATIONS INFORMATION DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the “hybrid” may be implemented. The split supply design (Figure typical two op-amp hybrid. The receive ...
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Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations ...
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... HIGH BAND RECEIVE -30 dBm DPSK OPERATION 1200 bit 3002 SIGNAL TO NOISE (dB) 73K302L BER vs PHASE JITTER 10 -2 HIGH BAND RECEIVE DPSK OPERATION 3002 11 10 PHASE JITTER (DEG.) ...
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... BER vs CARRIER OFFSET 10 -2 HIGH BAND RECEIVE DPSK OPERATION 3002 11.8 dB S/N C2 11 CARRIER OFFSET (HZ) -8 -12 27 Bell 212A, 103, 202 Single-Chip Modem ...
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Bell 212A, 103, 202 Single-Chip Modem MECHANICAL SPECIFICATIONS 28-Pin DIP 28-Pin PLCC 0.495 (12.573) 0.485 (12.319) PIN NO. 1 IDENT. 0.495 (12.573) 0.485 (12.319) 0.456 (11.650) 0.450 (11.430) 0.165 (4.191) 0.180 (4.572) 0.456 (11.650) 0.450 (11.430) 0.016 (0.406) 0.020 (0.508) ...
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... Bell 212A, 103, 202 Single-Chip Modem CAUTION: Use handling procedures necessary for a static sensitive component PLCC PINOUTS 23 ARE THE SAME THE 28-PIN DIP 28-Pin PLCC 73K302L-IH PACKAGING MARK 73K302L-IP 73K302L-IH 04/24/00- rev. D ...