ML7012 OKI [OKI electronic componets], ML7012 Datasheet

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ML7012

Manufacturer Part Number
ML7012
Description
2400 bps Single Chip Full Duplex Data Modem with Protocol
Manufacturer
OKI [OKI electronic componets]
Datasheet
GENERAL DESCRIPTION
The ML7012-04 is a single chip modem LSI device that enables data communication conforming to ITU-T
recommendations V.22bis, V.22, and V.21. This device is equipped with the error correction protocol function
conforming to MNP Class 4. (The MNP Class 4 can be used for V.22bis or V.22.)
The ML7012-04 consists of high speed DSP, analog front end, and digital logic circuit. In addition, this device
provides local analog loop testing, synchronous/asynchronous switching, dialing, and auto answering functions.
The ML7012-04 has a serial interface as an external interface. When integrated into the system, it is controlled
from a control CPU through a serial interface (e.g. UART). By connecting a level converter, the ML7012-04 can
easily implement a modem that can be controlled through the RS-232C interface.
FEATURES
* MNP is a registered trademark of Microcom Inc.
1 Semiconductor
ML7012-04
2400 bps Single Chip Full Duplex Data Modem with Protocol
Conforming to ITU-T Recommendations V.22 bis, V.22, and V.21: Asynchronous
Error correction function conforming to MNP Class 4
Serial interface: V.24 interface
AT commands (excluding automatic command speed detection)
Terminal data speed between DTE and DCE: 9600 bps, 2400 bps, 1200 bps, 300 bps
Character format: 10 bit/character
DTMF sending function
Pulse-dial control signal output
Call progress tone
Auto answering function
Built-in electronic HYB circuit (a line transformer can be directly coupled)
Single +3 V power supply
Power consumption: Typ. = 35 mA (V
Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: ML7012-04GA)
FEDL7012-04-01
DD
= 3.3 V)
This version: Sep. 2000
1/22

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ML7012 Summary of contents

Page 1

... The ML7012-04 has a serial interface as an external interface. When integrated into the system controlled from a control CPU through a serial interface (e.g. UART). By connecting a level converter, the ML7012-04 can easily implement a modem that can be controlled through the RS-232C interface. ...

Page 2

... PDN/RST Clock OSC0 generation OSC1 To each section TST2 to 0 TI8 to 0 TO10 to 0 VDD2, 1 GND2, 1 AFE Modulation/ demodulation Tone generation Tone detection SG Gen. FEDL 7012-04-01 ML7012-04 RLY2 RLY1 AOUT RCI – RCAO + TXAI – TXAN + – TXAP + – AIN + GSR SG SPK ...

Page 3

... DTR TI8 8 TO0 9 TO1 10 TO2 11 SPEED1 12 SPEED0 13 TI0 14 TI1 Note: Pins marked (NC) are no-connection pins which are left open. 64-Pin Plastic QFP FEDL 7012-04-01 ML7012-04 TXAP 48 TXAN 47 TXAI 46 RCAO 45 RCI 44 AOUT DDA OSC1 41 OSC0 40 TI7 39 TI6 38 TI5 34 NC ...

Page 4

... When PDN/RST = “0”, DSR outputs “1”. DTR I DTR (Data Terminal Ready) signal input pin CI (Calling Indicator) signal output pin (* When PDN/RST = “0”, CI outputs “1”. FEDL 7012-04-01 ML7012-04 Description Description 0: Space, 1: Mark 0: Space, 1: Mark 0: On, 1: Off 0: On, 1: Off 0: On, 1: Off 0: On, 1: Off ...

Page 5

... Input “1” while not detecting an incoming signal Fix this pin to "1" when a ring detector is not used. Speaker control signal output pin 0: speaker On SPK O 1: speaker Off When PDN/RST = “0”, SPK outputs “1”. FEDL 7012-04-01 Description Description ML7012-04 5/22 ...

Page 6

... GND2 Digital GND pin (*1) Pre-pause RLY1 RLY2 Line Connection (*2) RII CI Description Speed 1 Speed Description Description pin DD pin DD Dialing Communicating 150 ms One incoming signal FEDL 7012-04-01 ML7012-04 Speed 300 bps 1200 bps 2400 bps 9600 bps Command 400 ms 6/22 ...

Page 7

... DD SG pin 1 Between OSC0 and 800 OSC1 OSC0 and OSC1 pins — 02 — — Including temperature –80 characteristics — — — — FEDL 7012-04-01 ML7012-04 Rating Unit –0.3 to +5 500 –55 to +150 C Typ. Max. Unit — ...

Page 8

... Power-down mode *1 DDS –0 — IN FEDL 7012-04-01 ML7012- 2 – Min. Typ. Max. Unit — — 1 1000 µA — µA — µA V 0.99 V — ...

Page 9

... VON OFF ON GSR level *2 VOFF ON OFF t — OFF ON CDD t — ON OFF CDH ATDL GSR level CPDL GSR level FEDL 7012-04-01 ML7012- 2 – Min. Typ. Max. Unit — 10 — — — k 1080 — — — — 100 pF 1 ...

Page 10

... The communication mode to DTE with the V.24 interface is as follows: Terminal data speed: 9600/2400/1200/300 bps Character format: Listed below Start Bit Data Bit Characters CR Parity Stop Bit None Odd number Even number None FEDL 7012-04-01 ML7012-04 LF Character Length 10/22 ...

Page 11

... Selects the monitor speaker operation Always OFF M ATMn from dialing to line connection Always when connected with a remote modem O ATO Goes to data mode from on-line command mode. Function Initial Value FEDL 7012-04-01 ML7012-04 Note — — — — 1 — — 1 — 11/22 ...

Page 12

... Line connection CONNECT 1200 1200 bps Line connection CONNECT 2400 2400 bps o — o Dial tone detection NO DIAL TONE — Busy tone detection FEDL 7012-04-01 ML7012-04 Initial Value Note — 0 — — — — BUSY — 12/22 ...

Page 13

... None None Bi-directional control by CTS/RTS Selects extended result code Displays the normal result code. \V AT\ Displays the result code with the mode of the MNP connection None Function Initial Value FEDL 7012-04-01 ML7012-04 Note — 1 — 13/22 ...

Page 14

... Silence state cannot be detected. Connected at 2400 bps Connected at 9600 bps in normal mode Connected at 1200 bps in MNP mode Connected at 2400 bps in MNP mode Judged as PBX line Judged as a direct line Judged as a tone line Judged as a pulse line FEDL 7012-04-01 ML7012- Meaning 14/22 ...

Page 15

... No. from decimal 0 to 27, 34, and 35. <d> specifies the number to be set from decimal 0 to 255 number is specified at <n> and <d> regarded as “0”. (2) S register reading The format to read S registers is as follows: ATS<n>? <n> specifies the register No. from decimal 0 to 27, 34, and 35 number is specified at <n> regarded as “0”. FEDL 7012-04-01 ML7012-04 15/22 ...

Page 16

... Bit map register — 23 Bit map register — — Not used Sets the level attenuator of transmit carrier. 2 When 15 to 255 is input, value is fixed to 15. Sets the sending level attenuator of DTMF signal. 0 When 15 to 255 is input, value is fixed to 15. FEDL 7012-04-01 ML7012-04 Function 16/22 ...

Page 17

... Analog loop back test Function in 1 setting Breaks DSR signal operates by ITU-T. CD signal carrier detection &D1 & Not used Auto re-train enabled Not used FEDL 7012-04-01 ML7012-04 Command & Command &T8 loop back self- &T7 &T6 & ...

Page 18

... Function in 1 setting 0 1 &G1 & Parity 1 Parity 1 Mark 0 Odd No. Not used Not used Not used Responds to the remote digital loop back request. FEDL 7012-04-01 ML7012-04 Command & Extended 1 command M Command 1 &G3 & Parity 1 None &T4, &T5 ...

Page 19

... F R6 600 R7 R8 • The 2nd order LPF should be built to make fc approximately 5 kHz using the built-in amplifier R3, and C1 and C2. Numeric examples 1000 pF 220 pF • When V • When V FEDL 7012-04-01 ML7012-04 LINE 3 V, R5/ < R5/R4 1.6. DD 19/22 ...

Page 20

... Set the values by the crystal manufacture’s matching evaluation external clock is used, input it to OSC0 11.0592 MHz connected between OSC0 and GND, and OSC1 and GND vary with the load OSC0 R OSC OSC1 1 M FEDL 7012-04-01 ML7012-04 20/22 ...

Page 21

... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL 7012-04-01 ML7012-04 (Unit: mm) 21/22 ...

Page 22

... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL 7012-04-01 ML7012-04 Copyright 2000 Oki Electric Industry Co., Ltd. 22/22 ...

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