MT9075 MITEL [Mitel Networks Corporation], MT9075 Datasheet - Page 26

• Manufacturer Part Number: MT9075
• Description: E1 Single Chip Transceiver
• Manufacturer: MITEL [Mitel Networks Corporation]

MT9075A
4-154
(BPVE), CRC-4 errors (CRCE), FAS errors (FASE),
NFAS errors (NFSE), payload (PERR) and a loss of
signal error (LOSE). The LOSE function overrides
the HDB3 encoding function.
Per Time Slot Control
There are two per time slot control pages (page 07H
and 08H) occupying a total of 32 unique addresses.
Each address controls a matching timeslot on the 32
transmit channels (onto the line) and the equivalent
channel data on the receive (DSTo) data. For
example, address 0 of the first per time slot control
page contains program control for transmit timeslot 0
and DSTo channel 0.
Per Time Slot Looping
Any channel or combination of channels may be
looped from transmit (sourced from DSTi) to receive
(output on DSTo) STBUS channels. When bit 4
(LTSL) in the Per Time Slot Control Word is set the
data from the equivalent transmit timeslot is looped
back onto the equivalent receive channel.
Any channel or combination of channels may be
looped from receive (sourced from the line data) to
transmit (output onto the line) channels. When bit 5
(RTSL) in the Per Time Slot Control Word is set the
data from the equivalent receive timeslot is looped
back onto the equivalent transmit channel.
PRBS Testing
If the control bit ADSEQ is zero (from master control
page 02H address 13H - Access Control Word), any
channel or combination of transmit channels may be
programmed to contain a generated pseudo random
bit sequence (2
setting bit 3 (TTST) in the Per Time Slot Control
Word.
If the control bit ADSEQ is zero any combination of
receive channels may be connected to the PRBS
decoder (2
sequence causes the PRBS error counter to
increment. The receive channels are selected by
setting bit 2 (RRST) in the Per Time Slot Control
Word.
If the PRBS testing is performed in a metallic or
external looparound the Per Time Slot Control Words
with TTST (transmit test, bit 3) set should have
RRST (receive test, bit 2) set at the same time.
15
-1). Each error in the incoming
15
-1). The channels are selected by
A-law Milliwatt
If the control bit ADSEQ is one (from master control
page 02H - access control word), the A-law digital
milliwatt sequence (Table 10), defined by G.711, is
available to be transmit on any combination of
selected channels. The channels are selected by
setting bit 3 (TTST), in the Per Time Slot Control
Word.
The same sequence is available to replace received
data on any combination of DSTo channels. This is
accomplished by setting bit 2 (RRST) in the Per Time
Slot Control Word for the corresponding channel.
Message Mode
The transmit data on any of the transmit channels
may be sourced either from the equivalent DSTi
channel or from a dual port RAM programmed by the
microport. The address of each dual port RAM
memory location is uniquely associated with a
transmit channel number. When bit 7 (TXMSG) in the
Per Time Slot Control Word for that channel is set
the transmit data for the channel is sourced from
within the transmit message page dual port RAM (on
page 0FH and 10H).
Receive
microprocessor port. The Rx message mode dual
port RAMs (on page 11H and 12H) have a unique
address associated with each incoming line channel.
When the processor reads any of the 32 memory
locations, it reads the last byte received from the
corresponding channel.
Alarms
The following alarms are detected by the receiver.
Each may generate a maskable interrupt:
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0
0
0
0
1
1
1
•
Table 10 - A-Law Digital Milliwatt Pattern
Remote Alarm Indication (RAI) - bit 3 (A) of
the receive NFAS;
0
0
0
0
0
0
0
data
1
1
1
1
1
1
1
may
Preliminary Information
1
0
0
1
1
0
1
also
0
0
0
0
0
0
0
be
1
0
0
1
1
0
0
read
0
0
0
0
0
0
0
by
0
1
1
0
0
1
1
the