9DBL411B IDT [Integrated Device Technology], 9DBL411B Datasheet - Page 6

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9DBL411B

Manufacturer Part Number
9DBL411B
Description
Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
9DBL411BGILFT
Manufacturer:
IDT
Quantity:
20 000
IDT
1
2
3
4
5
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
6
7
8
9
cannot 'de-jitter' a noisy input clock. Values calculated per PCI SIG and per Intel Clock Jitter tool version 1.5
Notes on Electrical Characteristics (all measurements use 9LRS3187B as clock source and R
AC Electrical Characteristics - DIF Low Power Differential Outputs
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing centered around differential zero
Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
This figure refers to the maximum distortion of the input wave form.
Operation under these conditions is neither implied, nor guaranteed.
Maximum input voltage is not to exceed maximum VDD
The 9DBL411B has no PLL, so the part itself contributes very little jitter to the input clock. But this also means that the 9DBL411
Additive Cycle to Cycle Jitter
Additive Phase Jitter QPI133
Additive Phase Jitter - PCIe
Additive Phase Jitter - PCIe
9DBL411B
Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI
Additive Phase Jitter PCIe
®
Maximum Output Voltage
Differential Voltage Swing
Minimum Output Voltage
Crossing Point Variation
Falling Edge Slew Rate
Rising Edge Slew Rate
Crossing Point Voltage
Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI
Duty Cycle Distortion
Slew Rate Variation
Propagation Delay
Gen2 High Band
Gen2 Low Band
(6.4GBs, 12 UI)
DIF[3:0] Skew
PARAMETER
Gen1
t
t
t
phase_addPCIG2LO
t
phase_addPCIG2HI
phase_addQPI6G4
phase_addPCIG1
DIFJ
SYMBOL
V
DIF
D
V
XABSVAR
t
V
V
V
CYCDIS0
SLVAR
t
t
SWING
XABS
t
SLR
FLR
HIGH
LOW
PD
C2CADD
SKEW
High Band is 1.5MHz to Nyquist
Low Band is 10KHz to 1.5MHz
Single-ended Measurement
Single-ended Measurement
Single-ended Measurement
Differential Measurement,
Differential Measurement,
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Includes undershoot
Input to output Delay
Includes overshoot
1.5MHz < 22MHz
11MHz to 33MHz
fIN<=133.33MHz
CONDITIONS
Additive
(50MHz)
6
1200
-300
MIN
300
1.5
1.5
2.5
1150
MAX
0.16
0.07
0.04
550
140
3.5
20
15
50
4
4
3
6
Advance Information
S
ps Pk-Pk
=33ohms/C
ps rms
ps rms
ps rms
UNITS
V/ns
V/ns
mV
mV
mV
mV
mV
ps
ps
ns
%
%
NOTES
L
1,3,4
1,3,5
=2pF test load):
1,2
1,2
1,6
1,9
1,9
1,9
1,9
1
1
1
1
1
1
1
1645C—10/18/10

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