S3C70F2 Samsung semiconductor, S3C70F2 Datasheet - Page 21

• Manufacturer Part Number: S3C70F2
• Description: The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange
• Manufacturer: Samsung semiconductor

S3C70F2/C70F4/P70F4
(T
NOTES:
1.
2.
TIMING WAVEFORMS
Data retention supply voltage
Data retention supply current
Release signal set time
Oscillator stabilization wait
time
A
= – 40 C to + 85 C)
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-
up.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
(1)
RESET
V
DD
Parameter
STOP INSTRUCTION
EXECUTION OF
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
Symbol
V
I
t
t
DDDR
SREL
WAIT
DDDR
V
Released by RESET
Released by interrupt
DATA RETENTION MODE
DDDR
STOP MODE
Conditions
= 1.8 V
V
DDDR
–
–
Min
INTERNAL RESET
1.8
–
0
–
–
OPERATION
t
SREL
2
RESET
17
Typ
0.1
(2)
IDLE MODE
–
–
t
/ fx
WAIT
ELECTRICAL DATA
Max
OPERATING
MODE
5.5
10
–
–
–
Unit
ms
ms
V
A
s
14-7