S3C72N4 Samsung semiconductor, S3C72N4 Datasheet - Page 24

• Manufacturer Part Number: S3C72N4
• Description: The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange
• Manufacturer: Samsung semiconductor

S3C72N2/C72N4/P72N4
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P72N4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
NOTE: "0" means low level; "1" means high level.
V
V
TEST
RESET
V
Program Memory
Operating Voltage (V
OTP Programming Mode
Pin Configuration
EPROM Programmability
LC1
LC2
DD
V
5 V
Main Chip
DD
Pin Name
/ V
SS
Characteristic
(TEST)
12.5 V
12.5 V
12.5 V
Vpp
5 V
Table 15-2. Comparison of S3P72N4 and S3C72N2/C72N4 Features
SDAT
SCLK
V
RESET
V
DD
PP
DD
Pin Name
Table 15-1. Pin Descriptions Used to Read/Write the EPROM
)
(TEST)
/ V
REG/
MEM
SS
0
0
0
1
Table 15-3. Operating Mode Selection Criteria
4-Kbyte EPROM
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
V
64 QFP
User Program 1 time
Pin No.
DD
9/10
(A15-A0)
Address
13
16
0E3FH
0000H
0000H
0000H
7
8
= 5 V, V
PP
S3P72N4
I/O
I/O
I/O
During Programming
(TEST) = 12.5 V
I
I
I
R/
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
Serial clock pin. Input only pin.
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
Chip initialization
Logic power supply pin. V
+5 V during programming.
1
0
1
0
W
EPROM read
EPROM program
EPROM verify
EPROM read protection
2-K / 4-Kbyte mask ROM
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
64 QFP
Programmed at the factory
Function
S3C72N2/C72N4
DD
Mode
should be tied to
–
S3P72N4 OTP
15-3