IDTIDT71P71604167BQ IDT [Integrated Device Technology], IDTIDT71P71604167BQ Datasheet - Page 3

• Manufacturer Part Number: IDTIDT71P71604167BQ
• Manufacturer: IDT [Integrated Device Technology]

Pin Definitions
BW
BW
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Symbol
CQ, CQ
DQ[X:0]
R/ W
0
SA
2
SA
LD
ZQ
, BW
C
, BW
C
K
0
K
1,
3
Pin Function
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output Clock
Input/Output
Input Clock
Input Clock
Input Clock
Input Clock
Input
Input
Input
Input
Input
Input
Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven during a
clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a Read operation is not initiated or
operation in progress completes.
1M x 18 -- DQ[17:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during
remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the
corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW
Burst count address bit on x18 and x36 DDRll devices. This bit allows changing the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
Load Control Logic: Sampled on the rising edge of K.
Read or Write Control Logic. If LD is low during the rising edge of K, the R/ W indicates whether a new operation should be a read or
rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together
Positive Input Clock. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0]
Negative Input Clock. K is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0]
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be
used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output
impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly
valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When operating in a single
LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read
512K x 36 -- DQ[35:0]
write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written
512K x 36 -- BW
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated.
write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
when in single clock mode. All accesses are initiated on the rising edge of K.
when in single clock mode.
to V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
0
controls DQ[8:0] and BW
0
controls DQ[8:0], BW
1
1
controls DQ[17:9], BW
controls DQ[17:9]
6.42
3
If LD is low, a two word burst read or write operation will initiate as designated by
2
Description
controls DQ[26:18] and BW
3
controls DQ[35:27]
Commercial Temperature Range
6112 tbl 02a