5V49EE504NLGI8 IDT [Integrated Device Technology], 5V49EE504NLGI8 Datasheet - Page 11

• Manufacturer Part Number: 5V49EE504NLGI8
• Description: EEPROM PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: IDT [Integrated Device Technology]

PLL Loop Bandwidth:
Charge pump gain (Kφ⎞) = Ip / 2π
VCO gain (K
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
ωc = (Rz * Kφ * K
Fc = ωc / 2π
Note, the phase/frequency detector frequency (F
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (φm)
needs to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = (Cz + Cp)/(Rz * Cz * Cp)
φm = (360 / 2π) * [tan
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V49EE504
EEPROM PROGRAMMABLE CLOCK GENERATOR
VCO
) = 900 MHz/V * 2π
VCO
* Cz)/(M * (Cz + Cp))
-1
(ωc/ ωz) - tan
-1
(ωc/ ωp)]
PFD
) is
11
IDT5V49EE504
CLOCK SYNTHESIZER
REV F 022310