TFRA84J13DS0 AGERE [Agere Systems], TFRA84J13DS0 Datasheet - Page 4

• Manufacturer Part Number: TFRA84J13DS0
• Description: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
• Manufacturer: AGERE [Agere Systems]

Product Description, Revision 4
April 29, 2005
2.3 DS1/J1/E1 Framing (FRM) (3x28/21)
Note: Available only on 18 channels out of 84/63.
Agere Systems Inc.
28/21 DS1/J1/E1 channels.
Line coding: B8ZS, HDB3, ZCS, AMI.
DS1 framing modes: ESF, D4, SLC
and SF (F
E1 framing modes: G.704 basic and CRC-4 multiframe
consistent with G.706.
J1 framing modes: JESF (Japan).
Supports DS1 and E1 unframed and transparent trans-
mission format.
DS1 signaling modes: transparent; register and system
access for ESF 2-state, 4-state, and 16-state; D4 2-state,
4-state, and 16-state; SLC-96 2-state, 4-state, and
16-state; J-ESF handling groups maintenance and
signaling; VT 1.5 SPE 2-state, 4-state, 16-state.
E1 signaling modes: transparent; register and system
access for entire TS16 multiframe structure as per ITU
G.732.
Signaling debounce and change of state interrupt.
V5.2 Sa7 processing.
Alarm reporting and performance monitoring per AT&T
ANSI, ITU-T, and ETSI standards.
Facility data link features:
— HDLC or transparent access for either ESF or
— Register/stack access for SLC-96 transmit and receive
— Extended superframe (ESF): automatic transmission
— Register/stack access for all CEPT Sa bits transmit
HDLC features:
— HDLC or transparent mode.
— Programmable logical channel assignment: any time
— 64 logical channels in both transmit and receive
— Maximum channel data rate is 64 kbits/s.
— Minimum channel data rate is 4 kbits/s (DS1/FDL or
— 128-byte FIFO per channel in both transmit and
— Tx to Rx loopback supported.
DDS + FDL frame formats.
data.
of the ESF performance report messages (PRM).
Automatic transmission of the ANSI T1.403 ESF per-
formance report messages. Automatic detection and
transmission of the ANSI T1.403 ESF FDL bit-oriented
codes.
and receive data.
slot, any bit for ISDN D channel, also inserts/extracts
C-channels for V5.1, V5.2 interfaces.
direction (any framing format).
E1 Sa bit).
receive directions.
t
only).
®
-96, T1 DM DDS,
®
,
2.4 DS3/E3/DS2/E2/DS1/E1 Multirate Cross Con-
System interfaces:
— Concentration highway interface:
— Parallel system bus interface at 19.44 MHz for data
— Network serial multiplexed interface (NSMI) minimal
Configurable cross point interconnect for up to 84/63
DS1/E1 signals to/from the FRM, VTMPR, M13/E13,
TPG/TPM, DS1/E1 DJA, and 86 external I/O pins. Also
supports 21/12 DS2/E2 to/from external I/O pins from/to
the M13/E13 functional block.
Connects three DS3/E3 signals from the external pins to
the M13/E13 MUX.
Provides grooming capability for up to 168 (84 receive
plus 84 transmit) DS1/E1 connections between the FRM,
M13/E13, DS1/E1 DJA, and 86 bidirectional sets of pins.
This allows for cross connect grooming of any block sig-
nal port n to any other signal port m on a different block
or output pin, or on the same block in the case of a
groomed loopback.
Multicast operation (one to many) is supported for 168
sources and destinations.
Any mix of DS2, E2, DS3, or E3 signals can interconnect.
Multirate cross connect allows 16 x 3 E1 signals to/from
E13 modules from/to the framer, TPG/TPM, and external
pins.
There are 4 x 3 E2 signals to/from E13 from/to external
pins.
There are three E3 signals from/to the E13 functional
block to/from external pins.
Jitter attenuation can also be inserted in-line on any
channel. (Note that cascading of jitter attenuators is not
allowed.)
Standard network loopback or straight-away facility test-
ing is supported for DS1/E1 and DS3/E3. A DS1/E1 test-
pattern generator capable of injecting idle standards-
based, pseudorandom bit sequence test patterns, or AIS
(blue) alarm can replace any source or transmitter. A
test-pattern monitor that can detect/count bit errors in a
pseudorandom test sequence, or loss of frame or syn-
chronization, can replace any sink or receiver.
nect (MRXC) (x1)
and signaling: single clock and frame synchronizing
signals.
pin count serial interface at 51.84 MHz optimized for
data and IMA applications.
Single clock and frame synchronizing signals;
programmable clock and data rates at 8.192 MHz
and 16.384 MHz; programmable clock edges and
bit/byte offsets.
DS3/E3/DS2/E2/DS1/E1/DS0
TFRA84J13 Ultraframer
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