HI-1567CD HOLTIC [Holt Integrated Circuits], HI-1567CD Datasheet - Page 2

• Manufacturer Part Number: HI-1567CD
• Description: 5V MONOLITHIC DUAL TRANSCEIVERS
• Manufacturer: HOLTIC [Holt Integrated Circuits]

PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
The HI-1567 family of data bus transceivers contain differ-
ential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
TRANSMITTER
Data input to the transmitter section of these devices is
from the complimentary CMOS /TTL inputs TXA/B and
TXA/B
across a 140 ohm load. The transmitter is connected to the
bus via a 1:2.5 transformer whose secondary is connected
to two 52 ohm isolation resisters which feed the terminated
70 ohm bus. This will produce a nominal voltage on the bus
of 7.5 volts peak to peak.
PIN
10
12
13
14
15
16
17
18
19
15
11
1
2
3
4
5
6
7
8
9
. This produces a nominal 30V peak to peak signal
SYMBOL
TXINHB
TXINHA
RXENA
RXENB
GNDA
GNDB
VDDA
BUSA
BUSA
VDDB
BUSB
BUSB
RXB
RXB
RXA
RXA
TXB
TXB
TXA
TXA
analog output
analog output
analog output
analog output
power supply
power supply
power supply
power supply
FUNCTION
digital output
digital output
digital output
digital output
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
HOLT INTEGRATED CIRCUITS
+5 volt power for channel A
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and
Ground for channel A
+5 volt power for channel B
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and
Ground for channel B
Receiver B output, inverted
Receiver B outpot, non-invertedl
Transmit inhibit, channel B. If high BUSB,
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
Receiver A output, non-inverted
Transmit inhibit, channel A. If high BUSA,
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
HI-1567, HI-1568
2
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and
ther at a logic “1” or logic “0” simultaneously. A logic “1:” ap-
plied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
TXA/B
RECEIVER
The receiver is transformer coupled to the bus by a 1:1
transformer. Its differential input stage drives a filter and
threshold comparator. CMOS/TTL data is outputted at the
RXA/B and
The receiver outputs can both be forced to a logic "0"
(HI-1567) or logic “1” (HI-1568) by setting RXENA or
RXENB low.
RXA/B
DESCRIPTION
pins.
BUSB
BUSA
RXA
RXB
low (HI-1567) or High (HI-1568)
low (HI-1567) or High (HI-1568)
disabled
disabled
TXA/B
are ei-