HI-8783PDI HOLTIC [Holt Integrated Circuits], HI-8783PDI Datasheet - Page 2

• Manufacturer Part Number: HI-8783PDI
• Description: ARINC INTERFACE DEVICE 8-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
• Manufacturer: HOLTIC [Holt Integrated Circuits]

PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
The HI-8783 is a parallel to serial converter, which when
loaded with four eight bit parallel bytes, outputs the data as
a 32 bit serial word. Timing circuitry inserts a 4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word
is being transmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity
bit, inserted so as to make the 32 bit word have odd parity. If
the PARITY ENB pin is low, the 32nd bit will be the D7 bit of
the 4th byte.
Outputs are provided for both ARINC 429/575 (DATA ONE
and DATA ZERO pins), and ARINC 561 (561 DATA and
561 SYNC pins) type data.
A low signal applied to the
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
HI-8783 HI-8783 HI-8784
(20-pin) (22-pin) HI-8785
3-10
PIN
11
12
13
14
15
16
17
18
19
20
1
2
-
-
-
-
-
2-8,10
PIN
22
11
12
14
15
16
17
18
19
20
21
1
-
-
-
-
-
3-9,11
PIN
RESET
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
-
-
PARITY ENB digital input
DATA ZERO digital output Goes high for each ARINC bit output that is a “zero”
pin resets the HI-8783’s
DATA ONE
SYMBOL
561 SYNC
XMIT CLK
XMT RDY
561 DATA
TXAOUT
TXBOUT
RESET
SLP1.5
WRITE
GND
VCC
Dn
A0
V+
V-
HOLT INTEGRATED CIRCUITS
HI-8783, HI-8784, HI-8785
FUNCTION
power supply +5 volt rail,
digital output ARINC 561 Sync signal
digital inputs
power supply Ground
digital input
digital input
digital input
digital input
digital input
digital output Goes high if the buffer register is empty
power supply -10 volt rail
digital output Goes high for each ARINC bit output that is a “one”
analog output Line driver ouptut - A side
analog output Line driver output - B side
digital output Serial output for ARINC 561 data
power supply +10 volt rail
2
Parallel 8 bit Data Input
Byte address, A0=1 for 1st byte, A0=0 for 2nd, 3rd & 4th bytes
Selects the slope of the line driver. High = 1.5us
Write strobe, loads data on rising edge
Registers and sequencing logic initialized when low
Clock input for the transmitter
When high the 32nd bit output is odd parity
Input data can be loaded when the XMT RDY signal is
high, which indicates the input buffer register is empty. The
first 8 bit byte is the label byte and is loaded with the A0 in-
put high, which initializes the internal byte counter. The re-
maining three bytes are loaded with A0 in the low state.
Each 8 bit byte is loaded into the input buffer register by a
low pulse on the
fourth byte is loaded, the XMT RDY output goes low. The
contents of the input buffer register are transferred to the
output register during the fourth bit period of the gap. If the
fourth gap bit period of the previous word has already been
transmitted, the contents of the input buffer register will be
transferred to the output shift register during the first bit pe-
riod after the loading of the fourth byte, and the XMT RDY
output goes high.
After the output shift register is loaded, the data is shifted
out to the output logic in the order shown in figure 2.
The 561 SYNC output pulses low when the XMT CLK is low
during the 8th bit of the ARINC transmission.
The XMIT CLK is the same as the data rate.
DESCRIPTION
WRITE
input. (See figure 1). After the