K6X1008C2D-B Samsung semiconductor, K6X1008C2D-B Datasheet
K6X1008C2D-B
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K6X1008C2D-B Summary of contents
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... K6X1008C2D Family Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 Revised - Deleted 32-TSOP1-0820R Package Type. - Added Commercial product. 0.2 Revised - Added Lead Free 32-SOP-525 Product 0.3 Revised - Added Lead Free 32-TSOP1-0820F Product 1.0 Finalized - Changed I from 10mA to 5mA ...
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... Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 32-DIP-600, 32-SOP-525, 32-SOP-525, 32-TSOP1-0820F PRODUCT FAMILY Operating Product Family Temperature K6X1008C2D-B Commercial(0~70 C) K6X1008C2D-F Industrial(-40~85 C) K6X1008C2D-Q Automotive(-40~125 C) 1. The parameters are tested with 50pF test load PIN DESCRIPTION ...
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... Automotive Products(-40~125 C) Part Name Function K6X1008C2D-GQ55 32-SOP, 55ns, L K6X1008C2D-GQ70 32-SOP, 70ns, L K6X1008C2D-TQ55 32-TSOP-F, 55ns, L K6X1008C2D-TQ70 32-TSOP-F, 70ns, L Mode Power Deselected Standby Deselected Standby Output Disabled Active Read Active Write Active Unit Remark K6X1008C2D-B C K6X1008C2D-F C K6X1008C2D-Q Revision 1.0 September 2003 ...
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... CMOS SRAM Typ Max Unit 5.0 5 Vcc+0.5 - 0.8 V Min Max Unit - Min Typ Max Unit - =Vss to Vcc - Read - - 5 0.2V, CS Vcc-0.2V IH 0.4 2 0.4 K6X1008C2D K6X1008C2D K6X1008C2D Revision 1.0 September 2003 ...
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... WHZ Test Condition 1) CS Vcc-0.2V 1 K6X1008C2D-B 1) Vcc=3.0V, CS Vcc-0.2V K6X1008C2D-F 1 K6X1008C2D-Q See data retention waveform 5 CMOS SRAM =-40~125 Speed Bins Units 55ns 70ns Max Min Max - ...
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... K6X1008C2D Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address High-Z Data out NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6X1008C2D Family TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address Data in Data out (WE Controlled CW( CW(2) t WP(1) t AS( Data Valid t WHZ (CS Controlled CW(2) AS( WP( Data Valid ...
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... K6X1008C2D Family TIMING WAVEFORM OF WRITE CYCLE(3) Address Data in Data out NOTES (WRITE CYCLE write occurs during the overlap of a low CS CS going high and WE going low: A write end at the earliest transition among measured from the begining of write to the end of write. ...
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... K6X1008C2D Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) #32 13.60 0.20 0.535 0.008 #1 1. 0.075 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) #32 #1 20.87 0.822 20.47 0.806 +0.100 0.41 -0.050 0. +0.004 0.016 0.028 -0.002 42.31 MAX 1.666 41.91 0.20 1.650 0.008 0.46 0.10 0.018 0.004 1.52 2.54 0.10 0.060 0.100 0.004 #17 14.12 0.30 0.556 0.012 #16 2.74 0.20 MAX 0.108 0.008 3.00 0.118 0.20 0.008 1 ...
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... K6X1008C2D Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.50 0.0197 #16 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 10 CMOS SRAM Units: millimeters(inches) #32 0. 0.010 8.40 MAX 0.331 #17 1.00 0.05 0.10 MIN 0.039 0.002 0.004 1.20 MAX 0.047 +0.10 0.15 -0.05 +0.004 0.006 -0.002 0. 0.020 Revision 1.0 ...