74VHC157MX Fairchild Semiconductor, 74VHC157MX Datasheet - Page 2

• Manufacturer Part Number: 74VHC157MX
• Description: MULTIPLEXER QUAD 2IN 16SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr
• Type: Multiplexerr

Specifications of 74VHC157MX

• Circuit: 4 x 2:1
• Independent Circuits: 1
• Current - Output High, Low: 8mA, 8mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Multiplexer
• No. Of Channels: 4
• Ratio: 2
• Supply Voltage Range: 2V To 5.5V
• Logic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Family Type: VHC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1992 Fairchild Semiconductor Corporation
74VHC157 Rev. 1.2
Logic Symbols
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
E
H
L
L
L
L
S
X
H
H
L
L
Inputs
IEEE/IEC
I
H
X
X
X
L
0
I
X
H
X
X
L
1
Outputs
Z
H
H
L
L
L
2
Functional Description
The VHC157 is a quad 2-input multiplexer. It selects four
bits of data from two sources under the control of a
common Select input (S). The Enable input (E) is active-
LOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs. The VHC157 is the
logic implementation of a 4-pole, 2-position switch where
the position of the switch is determined by the logic
levels supplied to the Select input. The logic equations
for the outputs are shown below:
A common use of the VHC157 is the moving of data from
two groups of registers to four common output busses.
The particular register from which the data comes is
determined by the state of the Select input. A less obvi-
ous use is as a function generator. The VHC157 can
generate any four of the sixteen different functions of two
variables with one variable common. This is useful for
implementing gating functions.
Z
Z
Z
Z
a
b
c
d
= E • (I
= E • (I
= E • (I
= E • (I
1c
1a
1b
1d
• S + I
• S + I
• S + I
• S + I
0a
0b
0d
0c
• S)
• S)
• S)
• S)
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