74AHC257D,112 NXP Semiconductors, 74AHC257D,112 Datasheet

IC QUAD 2-IN MUX 3-ST 16SOIC

74AHC257D,112

Manufacturer Part Number
74AHC257D,112
Description
IC QUAD 2-IN MUX 3-ST 16SOIC
Manufacturer
NXP Semiconductors
Series
74AHCr
Type
Multiplexerr
Datasheet

Specifications of 74AHC257D,112

Circuit
4 x 2:1
Independent Circuits
1
Current - Output High, Low
8mA, 8mA
Voltage Supply Source
Single Supply
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Logical Function
Mux
Configuration
4 x 2:1
Number Of Inputs
8
Number Of Outputs
4
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
5.5V
Power Dissipation
500mW
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
16
Package Type
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AHC257D
74AHC257D
935265467112
1. General description
2. Features
The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and
the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data
appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch,
where the position of the switch is determined by the logic levels applied to input S. The
outputs are forced to a high-impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has
non-inverting (true) outputs.
I
I
I
I
I
I
I
I
1Y = OE
2Y = OE
3Y = OE
4Y = OE
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Rev. 02 — 9 May 2008
Balanced propagation delays
All inputs have Schmitt-trigger actions
Non-inverting data path
Inputs accept voltages higher than V
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
N
For 74AHC257: CMOS level
For 74AHCT257: TTL level
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
(1I1
(2I1
(3I1
(4I1
S + 1I0
S + 2I0
S + 3I0
S + 4I0
S)
S)
S)
S)
CC
Product data sheet

Related parts for 74AHC257D,112

74AHC257D,112 Summary of contents

Page 1

Quad 2-input multiplexer; 3-state Rev. 02 — 9 May 2008 1. General description The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC257 74AHC257D +125 C 74AHC257PW +125 C 74AHCT257 74AHCT257D +125 C 74AHCT257PW +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT257_2 Product data sheet 74AHC257; 74AHCT257 Description SO16 plastic small outline package; 16 leads; ...

Page 3

... NXP Semiconductors mga835 Fig 2. Logic symbol Fig 4. Logic diagram 74AHC_AHCT257_2 Product data sheet Fig 3. 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 OE S Rev. 02 — 9 May 2008 74AHC257; 74AHCT257 Quad 2-input multiplexer; 3-state MUX 001aad467 IEC logic symbol 001aad468 © NXP B.V. 2008. All rights reserved. ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin S 1 1I0 2 1I1 2I0 5 2I1 GND 3I1 10 3I0 4I1 13 4I0 74AHC_AHCT257_2 Product data sheet 74AHC257; 74AHCT257 1 S 1I0 2 1I1 257 ...

Page 5

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Control [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC257 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT257 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...

Page 7

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 OFF-state output current 5 supply current 5 input capacitance C output O capacitance 74AHCT257 V HIGH-level input voltage V LOW-level input voltage V HIGH-level ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC257 t propagation nI0, nI1 to nY; see pd delay nY; see enable time OE to nY; see disable time OE to nY; see ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHCT257 4 5 propagation nI0, nI1 to nY; see pd delay nY; see enable time OE to nY; see disable time OE to nY; see dis power MHz dissipation 4 outputs switching via ...

Page 10

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Data inputs and common data select input to output propagation delays OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...

Page 11

... NXP Semiconductors negative positive Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance load resistance test selection switch. Fig 8. Test circuitry for measuring switching times Table 9. Test data Type Input ...

Page 12

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... Document ID Release date 74AHC_AHCT257_2 20080509 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT257_1 20000403 74AHC_AHCT257_2 Product data sheet 74AHC257 ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...

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