C8051F392-A-GM Silicon Laboratories Inc, C8051F392-A-GM Datasheet

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C8051F392-A-GM

Manufacturer Part Number
C8051F392-A-GM
Description
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of C8051F392-A-GM

Lead_time
42
Pack_quantity
91
Comm_code
85423190

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Preliminary Rev. 0.71 8/12
Analog Peripherals
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On-Chip Debug
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Low Power
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Temperature Range
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Package
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
10-Bit ADC
Two 10-Bit Current Output DACs
Comparator
Precision Temperature Sensor
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
160 µA/MHz Active mode with 49 MHz internal
precision oscillator
200 nA Stop mode current
–40 to +85 °C (‘F37x)
–40 to +105 °C (‘F39x)
24-Pin QFN (‘F390/1/4/5 and ‘F37x)
20-Pin QFN (‘F392/3/6/7/8/9)
Programmable throughput up to 500 ksps
Up to 16 external inputs, programmable as single-
ended or differential
Reference from on-chip voltage reference, V
external VREF pin
Internal or external start of conversion sources
Supports output through resets for continuous
operation
Programmable hysteresis and response time
Configurable as interrupt or reset source
Accurate to ±2
user calibration
°
(‘F390/2/4/6/8 and ‘F370/4)
C across temperature range with no
INTERNAL OSCILLATOR
INTERRUPTS
M
COMPARATOR
A
U
X
49 MHz PRECISION
ISP FLASH
VOLTAGE
FLEXIBLE
+
16/8 kB
PERIPHERALS
500 ksps
Copyright © 2012 by Silicon Laboratories
HIGH-SPEED CONTROLLER CORE
50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU
ANALOG
VREF
10-bit
ADC
Temp Sensor
Temp Sensor
‘F390/2/4/6/8 &
DD
Precision
‘F370/4 Only
Current
or
10-bit
80 KHz LOW FREQUENCY
INTERNAL OSCILLATOR
DAC
Current
CIRCUITRY
10-bit
8051 CPU
(50 MIPS)
DAC
DEBUG
High-Speed 8051 µC Core
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Memory
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Digital Peripherals
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Clock Sources
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Supply Voltage 1.8 to 3.6 V
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SMBus0
SMBus1
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
UART
PCA0
PCA1
PCA2
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Up to 1 kbytes internal data RAM (256 + 768)
Up to 16 kB Flash; In-system programmable in 512-
byte Sectors
512 bytes of byte-programmable EEPROM; 1 mil-
lion write/erase cycles (‘F37x)
21 or 17 Port I/O
UART, 2 SMBus (I
ports
Six general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules and PWM functionality
49 MHz ±2% precision internal oscillator
80 kHz low-frequency, low-power oscillator
External oscillator: Crystal, RC, C, or CMOS clock
Can switch between clock sources on-the-fly; useful
in power saving modes
Built-in voltage supply monitor
SPI
DIGITAL I/O
Supports crystal-less UART operation
Low-power suspend mode with fast wake time
POR
*P2.1–2.4 QFN24 Only
1024 B
SRAM
EEPROM
512 B
Port 0
Port 1
P2.1–
P2.4*
P2.0
C8051F39x/37x
WDT
2
C compatible), and SPI serial
C8051F39x/37x

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