SI5369A-C-GQ Silicon Laboratories Inc, SI5369A-C-GQ Datasheet

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SI5369A-C-GQ

Manufacturer Part Number
SI5369A-C-GQ
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5369A-C-GQ

Lead_time
84
Pack_quantity
90
Comm_code
85423990

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Part Number
Manufacturer
Quantity
Price
Part Number:
SI5369A-C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5369A-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
A
A
Features
Applications
Description
The Si5369 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs
ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The
outputs are divided down separately from a common source. The Si5369 input
clock frequency and clock multiplication ratio are programmable through an I
SPI interface. The Si5369 is based on Silicon Laboratories' third-generation
DSPLL
attenuation in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level.
Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.
Preliminary Rev. 0.4 5/11
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 300 fs rms
(50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter
specifications
Four clock inputs with manual or
automatically controlled hitless
switching and phase build-out
Supports holdover and freerun
modes of operation
SONET frame sync switching and
regeneration
SONET/SDH OC-48/STM-16/OC-
192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10G FC line cards
ITU G.709 and custom FEC line cards
Wireless repeaters/wireless backhaul
Data converter clocking
N Y
TTENUATOR
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
®
- F
technology, which provides any-frequency synthesis and jitter
REQUENCY
P
Copyright © 2011 by Silicon Laboratories
RECISION
Five clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (253/226, 239/237,
255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjust
I
On-chip voltage regulator for 1.8 V
±5%, 2.5 V ±10%, or 3.3 V ±10%
operation
Small size: 14 x 14 mm 100-pin
TQFP
Pb-free, RoHS compliant
2
C or SPI programmable settings
OTN/WDM Muxponder, MSPP,
ROADM line cards
SONET/SDH + PDH clock
synthesis
Test and measurement
Synchronous Ethernet
Broadcast video
C
L O C K
2
C or
M
ULTIPLIER
CS0_C3A
INT_ALM
VDD
GND
GND
GND
VDD
GND
GND
GND
RST
VDD
C1B
C2B
C3B
NC
NC
NC
NC
XA
XB
NC
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
1
2
3
4
5
6
7
8
9
26
Ordering Information:
99
27
98
28
97
29
Pin Assignments
96
30
95
31
See page 77.
32
94
33
93
34
92
Si5369
91
35
90
Si5369
GND PAD
36
89
37
88
38
39
87
/J
86
40
41
85
84
42
83
43
82
44
I T T E R
45
81
80
46
79
47
48
78
77
49
76
50
Si5369
75
74
73
72
71
70
69
68
67
65
66
64
63
62
60
59
58
57
56
55
54
53
52
51
61
NC
NC
NC
NC
SDI
A2_SS
A1
A0
NC
NC
GND
GND
VDD
VDD
SDA_SDO
SCL
C2A
C1A
CS1_C4A
NC
GND
GND
NC
NC
NC

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