IDT72V90823PF8 IDT, Integrated Device Technology Inc, IDT72V90823PF8 Datasheet - Page 16

• Manufacturer Part Number: IDT72V90823PF8
• Description: IC DGTL SW 2048X2048 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V90823PF8

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V90823PF8

TABLE 13 — CONNECTION MEMORY BITS
NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel
TABLE 14 — CAB BIT PROGRAMMING FOR DIFFERENT DATA RATES
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
10-8,7
6-0
Bit
and stream associated with this location.
LPBK
15
14
13
12
11
15
(1)
(1)
LPBK
(Per Channel Loopback)
V/C
(Variable/Constant
Throughput Delay)
PC
(Processor Channel)
CCO
(Control Channel Output)
OE
(Output Enable)
SAB3-0
(Source Stream Address Bits)
CAB6-0
(Source Channel Address Bits)
V/C
14
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Data Rate
PC
13
Name
CCO
12
OE
11
When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.
This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a
per-channel basis.
When 1, the contents of the connection memory are output on the corresponding output channel and stream.
Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection
memory are the data memory address of the switched input channel and stream.
This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions
normally. When 0, the output driver is in a high-impedance state.
This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
The binary value is the number of the data stream for the source of the connection.
The binary value is the number of the channel for the source of the connection.
SAB3
10
SAB2
9
SAB1
CAB Bits Used to Determine the Source Channel of the Connection
8
SAB0
7
16
CAB6
CAB6 to CAB0 (128 channel/input stream)
CAB4 to CAB0 (32 channel/input stream)
CAB5 to CAB0 (64 channel/input stream)
6
Description
CAB5
5
CAB4
4
CAB3
3
COMMERCIAL TEMPERATURE RANGE
CAB2
2
CAB1
1
CAB0
0