CY7C09089 Cypress Semiconductor Corporation., CY7C09089 Datasheet
CY7C09089
Manufacturer Part Number
CY7C09089
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C09089
Case
QFP
Date_code
05+
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Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *B
Features
Notes:
1. See page 6 for Load Conditions.
2. I/O
3. A
• True Dual-Ported memory cells which allow simulta-
• 6 Flow-Through/Pipelined devices
• 3 Modes
• Pipelined output mode on both ports allows fast
• 0.35-micron CMOS for optimum speed/power
Logic Block Diagram
R/W
OE
CE
CE
FT/Pipe
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
— 32K x 8/9 organizations (CY7C09079V/179V)
— 64K x 8/9 organizations (CY7C09089V/189V)
— 128K x 8/9 organizations (CY7C09099V/199V)
— Flow-Through
— Pipelined
— Burst
100-MHz operation
0
0
–A
–A
0
0L
L
0L
1L
–I/O
L
L
L
14
–I/O
[3]
14/15/16L
for 32K, A
7
L
L
for x8 devices, I/O
[2]
L
7/8L
0
–A
15/16/17
15
for 64K, and A
0
–I/O
8/9
0/1
8
0/1
1
0
1
Counter/
Address
Register
for x9 devices.
Decode
0
–A
16
0
for 128K devices.
•
3901 North First Street
Control
I/O
True Dual-Ported
RAM Array
Synchronous Dual-Port Static RAM
• High-speed clock to data access 6.5
• 3.3V low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available
(max.)
— Active= 115 mA (typical)
— Standby= 10 µA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
•
3.3V 32K/64K/128K x 8/9
San Jose
0
Counter/
Address
Register
Decode
,
CY7C09079V/89V/99V
CY7C09179V/89V/99V
CA 95134
0/1
1
1
0
0/1
8/9
Revised May 18, 2005
15/16/17
•
[1]
/7.5
408-943-2600
A
I/O
[1]
0
–A
/9/12 ns
0R
CNTRST
FT/Pipe
CNTEN
14/15/16R
–I/O
[3]
ADS
R/W
CLK
CE
CE
OE
[2]
7/8R
0R
1R
R
R
R
R
R
R
R
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