A3P030-1QNG132I Actel, A3P030-1QNG132I Datasheet

A3P030-1QNG132I

Manufacturer Part Number

A3P030-1QNG132I

Description

QFN 132/FPGA, 768 CLBS, 30000 GATES, 350 MHz

Manufacturer

Actel

Datasheet

1.A3P030-2QNG132I.pdf (218 pages)

Specifications of A3P030-1QNG132I

Lead_time

Pack_quantity

348

Comm_code

85423990

Current page: 1 of 218
Download datasheet (7Mb)

October 2009

ProASIC3 Flash Family FPGAs

with Optional Soft ARM

Features and Benefits

High Capacity

Reprogrammable Flash Technology

High Performance

In-System Programming (ISP) and Security

Low Power

High-Performance Routing Hierarchy

Advanced I/O

Table 1 • ProASIC3 Product Family

ProASIC3 Devices

Cortex-M1 Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. Refer to the

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the

5. The M1A3P250 device does not support this package.

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

• Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

• Segmented, Hierarchical Routing and Clock Structure

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

QFN

VQFP

TQFP

PQFP

FBGA

† A3P015 and A3P030 devices do not support this feature.

Standard (AES) Decryption (except ARM-enabled ProASIC

devices) via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

Cortex-M1

†

product brief for more information.

A3P015

QN68

15 k

128

384

1 k

–

QN48, QN68,

†

A3P030

QN132

VQ100

30 k

256

768

1 k

Support

–

A3P060

QN132

VQ100

TQ144

FG144

CS121

1,536

60 k

512

Yes

1 k

‡ Supported only by A3P015 and A3P030 devices.

A3P125

Clock Conditioning Circuit (CCC) and PLL

Embedded Memory

ARM Processor Support in ProASIC3 FPGAs

QN132

VQ100

TQ144

PQ208

FG144

125 k

1,024

3,072

133

• Wide Range Power Supply Voltage Support per JESD8-B,

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

• Six CCC Blocks, One with an Integrated PLL

• Configurable

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• True Dual-Port SRAM (except ×18)

• M1 ProASIC3 Devices—ARM

Yes

1 k

ProASIC3E Flash Family FPGAs

Allowing I/Os to Operate from 2.7 V to 3.6 V

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X

2.5 V / 5.0 V Input

M-LVDS (A3P250 and above)

Capabilities and External Feedback

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

Available with or without Debug

FG144/256

M1A3P250

QN132

A3P250

VQ100

PQ208

250 k

2,048

6,144

157

Yes

1 k

I/O

Phase-Shift,

†

FG144/256/

M1A3P400

Standards:

A3P400

PQ208

400 k

9,216

194

484

Yes

1 k

–

handbook.

Cortex™-M1 Soft Processor

†

M1A3P600

FG144/256/

Multiply/Divide,

LVTTL,

and Drive Strength

A3P600

†

13,824

PQ208

600 k

108

Yes

235

484

‡

1 k

–

LVCMOS

†

and LVCMOS

M1A3P1000

FG144/256/

A3P1000

24,576

PQ208

1 M

144

300

484

Yes

1 k

–

v1.3

3.3 V /

Delay

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