MC74ACT139DR2G ON Semiconductor, MC74ACT139DR2G Datasheet - Page 2

• Manufacturer Part Number: MC74ACT139DR2G
• Description: IC DECODER/DEMUX DUAL 1:4 16SOIC
• Manufacturer: ON Semiconductor
• Series: 74ACTr
• Type: Decoder/Demultiplexerr

Specifications of MC74ACT139DR2G

• Circuit: 1 x 2:4
• Independent Circuits: 2
• Current - Output High, Low: 24mA, 24mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Logical Function: Decoder/Demux
• Logic Family: ACT
• Number Of Elements: 2
• Polarity: Inverting
• Number Of Inputs: 2
• Number Of Outputs: 4
• Output Type: Open Drain
• Propagation Delay Time: 11ns
• Package Type: SOIC
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Quiescent Current: 8uA
• Technology: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74ACT139DR2G; MC74ACT139DR2GOSTR

1−of−4 decoder/demultiplexer. The device has two
independent decoders, each of which accepts two binary
weighted inputs (A
exclusive active−LOW outputs (O
an active−LOW enable (E). When E is HIGH all outputs are
forced HIGH. The enable can be used as the data input for
a 4−output demultiplexer application. Each half of the
MC74AC139/74ACT139 generates all four minterms of
two variables. These four minterms are useful in some
applications, replacing multiple gate functions as shown in
Figure 4, and thereby reducing the number of packages
required in a logic network.
The MC74AC139/74ACT139 is a high−speed dual
FUNCTIONAL DESCRIPTION
0
−A
1
) and provides four mutually
NOTE:
0
0a
0
E
−O
a
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
3
0
). Each decoder has
1a
0
2a
Figure 3. Logic Diagram
Figure 2. Logic Symbol
A
http://onsemi.com
0a
0
O
O
DECODER b
DECODER a
A
3a
E A
E A
0
0
1a
O
O
1
1
2
0
0
O
O
2
2
A
0
A
O
0b
O
1
1
3
3
E
b
A
A
A
A
A
A
A
A
E
E
E
E
0
1
0
1
0
1
0
1
0
1b
Figure 4. Gate Functions (Each Half)
0
2b
A
0b
0
O
O
O
O
A
3b
0
1
2
3
1b
A
A
A
A
A
A
A
A
E
E
E
E
0
1
0
1
0
1
0
1
O
O
O
O
0
1
2
3