HI-3282PJI HOLTIC [Holt Integrated Circuits], HI-3282PJI Datasheet - Page 4

• Manufacturer Part Number: HI-3282PJI
• Description: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (con't)
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
The ARINC 429 specification contains the following timing
specification for the received data:
BIT TIMING
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
PULSE FALL TIME
PULSE RISE TIME
PULSEWIDTH
BIT RATE
DECODER
CONTROL
BITS
SEL
D/R
EN
ZEROS
ONES
NULL
/
100K BPS ± 1% 12K -14.5K BPS
CONTROL
CONTROL
HIGH SPEED
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
ENABLE
LATCH
5 µsec ± 5%
MUX
EOS
BITS 9 & 10
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
34.5 to 41.7 µsec
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
FIGURE 2.
32 BIT SHIFT REGISTER
32 TO 16 DRIVER
HOLT INTEGRATED CIRCUITS
32 BIT LATCH
TO PINS
RECEIVER BLOCK DIAGRAM
HI-3282
4
WORD GAP
BIT CLOCK
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word
program bits or if the receiver decoder is disabled, then EOS
clocks the data ready flag flip flop to a "1",
will go low. The data flag for a receiver will remain low until after
both
accomplished by activating
to retrieve the first byte and activating
retrieve the second byte.
EN2
If another ARINC word is received, and a new EOS occurs
before the two bytes are retrieved, the data is overwritten by the
new word.
DATA
START
retrieves data from receiver 2.
ARINC bytes from that receiver are retrieved. This is
CONTROL
BIT BD14
PARITY
CHECK
WORD GAP
SEQUENCE
DETECTION
CONTROL
ERROR
TIMER
32ND
BIT
EOS
END
ERROR
CLOCK
SEQUENCE
ENI
COUNTER
BIT CLOCK
END OF
OPTION
CLOCK
EN
AND
BIT
retrieves data from receiver 1 and
with SEL, the byte selector, low
CLOCK
D/R1
EN
with SEL high to
or
D/R2
CLK
(or both)