K4S643232E-TE50 SAMSUNG [Samsung semiconductor], K4S643232E-TE50 Datasheet
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K4S643232E-TE50
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K4S643232E-TE50 Summary of contents
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... K4S643232E-TE SDRAM 512K x 32bit x 4 Banks Extended Temperature Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM LVTTL(3.3V) 86-TSOP Revision 1.4 December 2001 - 1 - CMOS SDRAM Rev. 1.4 (Dec. 2001) ...
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... Revision 1.3 (October 24, 2001) • Removed CAS Latency 1 from the spec. Revision 1.2 (August 7, 2001) - • Added CAS Latency 1 Revision 1.1 (July 6, 2001) • Added K4S643232E-T/S(E/N)50 Revision 1.0 (April 6, 2001) Revision 0.0 (March 21, 2001) • Initial draft • Extended temperature (- • 3.3V Power supply (VDD &VDDQ) • ...
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... LCBR CLK CKE GENERAL DESCRIPTION The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle ...
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... K4S643232E-TE/N PIN CONFIGURATION (Top view TSOP DQM0 A10/AP DQM2 DQ16 V DQ17 DQ18 V DQ19 DQ20 V DQ21 DQ22 V DQ23 DQ0 DDQ DQ1 4 83 DQ2 SSQ DQ3 7 80 DQ4 DDQ DQ5 10 77 DQ6 11 76 ...
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... K4S643232E-TE/N PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address 0 10 BA0,1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 3 Data input/output mask DQ ~ Data input/output Power supply/ground ...
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... AC.The overshoot voltage duration (min) = -2.0V AC. The undershoot voltage duration Any input DDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The V condition of K4S643232E-60 is 3.135V ~ 3.6V DD CAPACITANCE (V = 3.3V Pin Clock RAS, CAS, WE, CS, CKE, DQM Address ...
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... Operating Current I CC4 (Burst Mode) Refresh Current I CC5 Self Refresh Current I CC6 1. Unless otherwise notes, Input level is CMOS(V Notes : 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232E-E** 5. K4S643232E-N - +85 A CAS Test Condition Latency Burst Length = (min (min ...
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... Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Output 870 (Fig output load circuit 1. The V condition of K4S643232E-60 is 3.135V ~ 3.6V Notes : DD OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter CAS Latency CLK cycle time ...
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... K4S643232E-TE/N Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change case of row precharge interrupt, auto precharge and read burst stop. ...
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... K4S643232E-TE/N SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable Burst Stop ...
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... K4S643232E-TE/N MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address / Function RFU RFU Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length Length Burst 1 Single Bit POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations ...
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... K4S643232E-TE/N BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address Sequential ...