IC42S16800 ICSI [Integrated Circuit Solution Inc], IC42S16800 Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
IC42S16800
Manufacturer Part Number
IC42S16800
Description
4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IC42S16800.pdf
(69 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IC42S16800-6TG
Manufacturer:
EUPEC
Quantity:
23
Part Number:
IC42S16800-6TG
Manufacturer:
ICSI
Quantity:
20 000
Company:
Part Number:
IC42S16800-7T
Manufacturer:
ICSI
Quantity:
2 206
Company:
Part Number:
IC42S16800-7T
Manufacturer:
ICSI
Quantity:
2 206
Company:
Part Number:
IC42S16800-7T
Manufacturer:
ST
Quantity:
123
Part Number:
IC42S16800-7T
Manufacturer:
ICSI
Quantity:
20 000
Company:
Part Number:
IC42S16800-7TG
Manufacturer:
DIODES
Quantity:
20 000
Part Number:
IC42S16800D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IC42S16800E-7TL
Manufacturer:
ISSI
Quantity:
20 000
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first D
WRITE to READ Command Interval
Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
24
Command
CAS latency =2
DQ
Command
CAS latency =3
DQ
CLK
T0
WRITE A
Write A
DA0
DA0
1 cycle
T1
Read B
Read B
Hi-Z
Hi-Z
T2
T3
QB0
T4
OUT
QB1
QB0
.
T5
Integrated Circuit Solution Inc.
QB2
QB1
T6
QB3
QB2
T7
Burst lengh=4
DR023-0E 6/11/2004
QB3
T8