54F407DM NSC [National Semiconductor], 54F407DM Datasheet - Page 2

• Manufacturer Part Number: 54F407DM
• Description: DATA ACCESS REGISTER
• Manufacturer: NSC [National Semiconductor]

Unit Loading Fan Out
Functional Description
The ’F407 contains a 4-bit slice of three Registers (R
a 4-bit Adder a TRI-STATE Address Output Buffer (X
and a separate Output Register with TRI-STATE buffers
(O
data bus (refer to the Block Diagram) The DAR performs
sixteen instructions selected by I
tion Table
The ’F407 operates on a single clock CP and EX are inputs
to a 2-input active LOW AND gate For normal operation EX
is brought LOW while CP is HIGH A microcycle starts as the
clock goes HIGH Data inputs D
Adder as one of the operands Three of the four instruction
lines (I
to be used as the other operand The LOW-to-HIGH CP
transition writes the result from the Adder into a register
(R
H
L
Pin Names
D
I
CI
CO
CP
EX
EO
EO
X
O
0
e
e
0
0
I
H
H
H
H
H
H
H
H
0
L
L
L
L
L
L
L
L
–I
0
0
3
–X
–D
–O
–R
X
0
–O
LOW Voltage Level
3
HIGH Voltage Level
3
3
3
1
2
3
) and into the output register provided EX is LOW If
) allowing output of the register contents on the
–I
2
–I
Data Inputs (Active LOW)
Instruction Word Inputs
Carry Input (Active LOW)
Carry Output (Active LOW)
Clock Input (L-H Edge-Triggered)
Execute Input (Active LOW)
Address Output Enable Input (Active LOW)
Data Output Enable Input (Active LOW)
Address Outputs
Data Outputs (Active LOW)
3
I
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
) select which of the three registers if any is
2
Instruction
I
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
1
Description
0
0
–I
–D
3
I
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
0
3
as listed in the Func-
are applied to the
Combinatorial Function
R
R
R
R
R
R
R
R
R
D Plus CI
R
D Plus CI
R
R
R
D Plus CI
Available on the X-Bus
0
0
0
0
0
0
1
1
2
0
2
2
1
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
0
0
–R
–X
Function Table
284 (100) 26 7 (13 3)
284 (100) 26 7 (13 3)
2
3
)
)
20 13 3 (0 67)
HIGH LOW
2
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
1 0 0 67
U L
the I
result from the Adder to the TRI-STATE Buffer controlling
the address bus (X
’F407 is organized as a 4-bit register slice The active LOW
CI and CO lines allow ripple-carry expansion over longer
word lengths
In a typical application the register utilization in the DAR
may be as follows R
the Stack Pointer (SP) for memory resident stacks and R
contains the operand address For an instruction Fetch PC
can be gated on the X-Bus while it is being incremented
(i e D-Bus
tive address for execution which is displaced from the PC
the displacement can be added to the PC and loaded into
R
2
during the next microcycle
0
instruction input is HIGH the multiplexer routes the
e
b
b
1) If the fetched instruction calls for an effec-
54F
5 7 mA (2 mA) 16 mA (8 mA)
5 7 mA (2 mA) 16 mA (8 mA)
R
R
R
R
D Plus CI
D Plus CI
R
D Plus CI
0 4 mA 8 mA (4 mA)
0
0
0
1
2
0
20 A
20 A
20 A
20 A
20 A
20 A
20 A
Output I
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
Plus D Plus CI
–X
Sequential Function Occurring
0
Input I
on the Next Rising CP Edge
3
is the Program Counter (PC) R
) independent of EX and CP The
b
b
b
b
b
b
b
IH
OH
0 4 mA
0 4 mA
0 4 mA
0 4 mA
0 4 mA
0 4 mA
0 4 mA
R
R
R
I
IL
I
2
0
1
OL
and 0-Register
and 0-Register
and 0-Register
R
R
R
R
R
0
1
2
1
2
and 0-Register
and 0-Register
and 0-Register
and 0-Register
and 0-Register
1
is
2