54F410 NSC [National Semiconductor], 54F410 Datasheet - Page 2

• Manufacturer Part Number: 54F410
• Manufacturer: NSC [National Semiconductor]

Unit Loading Fan Out
Functional Description
Write Operation When the three control inputs Write En-
able (WE) Chip Select (CS) and Clock (CP) are LOW the
information on the data inputs (D
memory location selected by the address inputs (A
the input data changes while WE CS and CP are LOW the
contents of the selected memory location follow these
changes provided setup and hold time criteria are met
Block Diagram
Pin Names
A
D
CS
OE
WE
CP
Q
0
0
0
–A
–D
–Q
3
3
3
Address Inputs
Data Inputs
Chip Select Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Clock Input (Outputs Change on
LOW-to-HIGH Transition)
TRI-STATE Outputs
Description
0
–D
3
) is written into the
0
–A
150 40 (33 3)
3
HIGH LOW
) If
1 0 1 0
1 0 1 0
1 0 2 0
1 0 1 0
1 0 1 0
1 0 2 0
U L
2
Read Operation Whenever CS is LOW and CP goes from
LOW-to-HIGH the contents of the memory location select-
ed by the address inputs (A
the Output Register
The (OE) input controls the output buffers When OE is
HIGH the four outputs (Q
OFF state when OE is LOW the outputs are determined by
the state of the Output Register
54F 74F
b
3 mA 24 mA (20 mA)
20 A
20 A
20 A
20 A
20 A
20 A
Output I
Input I
b
b
b
b
b
b
IH
OH
0 6 mA
0 6 mA
1 2 mA
0 6 mA
0 6 mA
1 2 mA
I
IL
I
OL
0
–Q
0
3
–A
) are in a high impedance or
3
) are edge-triggered into
TL F 9538– 4