SMC256BFY6E NUMONYX [Numonyx B.V], SMC256BFY6E Datasheet - Page 49
SMC256BFY6E
Manufacturer Part Number
SMC256BFY6E
Description
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.SMC256BFY6E.pdf
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SMCxxxBF
Table 42.
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
PIO Byte Data Register (Selected Using
DMA Word Data Register
Set Features Command)
PIO Word Data Register
Data Register
Data Register Access
Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the Status register. The bits are defined in
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
Bit 7 (BBK)
This bit is set when a Bad Block is detected.
Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
Bit 5
This bit is ‘0’.
Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
Bit 3
This bit is ‘0’.
Bit 2 (Abort)
This bit is set if the command has been aborted because of a Card status condition (Not
Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is ‘0’.
Bit 0 (AMNF)
This bit is set when there is a general error.
(True IDE mode)
–CS1
1
1
1
–CS0
0
1
0
A0
X
0
0
-DMACK
1
0
1
Offset
Table 43
0h
0h
X
CF-ATA registers
This register
D15 to D0
D15 to D0
Data Bus
D7 to D0
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