SMC128AF NUMONYX [Numonyx B.V], SMC128AF Datasheet - Page 22
SMC128AF
Manufacturer Part Number
SMC128AF
Description
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.SMC128AF.pdf
(82 pages)
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Command interface
5
Figure 2.
1. D
Table 16.
22/82
tc(R)
ta(A)
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
tsu(A)
Symbol
the -WE signal must be de-asserted between consecutive cycle operations.
OUT
D0 to D15 (D
signifies data provided by the CompactFlash memory card to the system. The -CE signal or both the -OE signal and
–REG
Address Inputs
–CE2/–CE1
–OE
Command interface
There are two types of bus cycles and timing sequences that occur in the PCMCIA type
interface, direct mapped I/O transfer and memory access.
Table
Figure
write timing diagrams.
Note, the wait width time is intentionally less than the PCMCIA specification of 12 µs. Its
maximum value can be determined from the card information structure.
Attribute memory Read timing diagram
Attribute memory Read timing
t
t
t
t
t
t
t
t
t
t
AVAV
AVQV
ELQV
GLQV
EHQZ
GHQZ
ELQNZ
GLQNZ
AXQX
AVGL
OUT
IEEE symbol
)
19,
2,
Figure
Table
20,
ten(OE)
tsu(A)
3,
Speed version
Figure
Table 21
ten(CE)
Read Cycle time
Address Access time
CE Access time
OE Access time
Output Disable time from CE
Output Disable time from OE
Output Enable time from CE
Output Enable time from OE
Data Valid from Address Change
Address Setup time
ta(A)
ta(CE)
ta(OE)
4,
and
Figure
Table 22
5,
Parameter
Figure
VALID
tc(R)
show the read and write timing parameters.
6,
Figure 7
VALID
and
Table
tv(A)
Figure 8
16,
Min
300
30
5
5
0
Table
show the read and
300 ns
tdis(CE)
17,
tdis(OE)
Max
300
300
150
100
100
Table
SMCxxxAF
AI10080
18,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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