K4H560838F-UC SAMSUNG [Samsung semiconductor], K4H560838F-UC Datasheet - Page 3

• Manufacturer Part Number: K4H560838F-UC
• Description: 256Mb F-die DDR400 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

DDR SDRAM 256Mb F-die (x8, x16)
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
•
*CL : CAS Latency
Ordering Information
Operating Frequencies
RoHS compliant
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
CL-tRCD-tRP
Speed @CL3
K4H560838F-UCCC
K4H561638F-UCCC
K4H560838F-UCC4
K4H561638F-UCC4
Part No.
Pb-Free
- CC(DDR400@CL=3)
package
200MHz
3 - 3 - 3
16M x 16
32M x 8
Org.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
- C4(DDR400@CL=3)
200MHz
3 - 4 - 4
Max Freq.
Interface
SSTL2
SSTL2
Rev. 1.1 August. 2003
DDR SDRAM
66pin TSOP II
66pin TSOP II
Package