SSD1854U ETC [List of Unclassifed Manufacturers], SSD1854U Datasheet - Page 31

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SSD1854U

Manufacturer Part Number
SSD1854U
Description
LCD Segment / Common Driver with Controller CMOS
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
SSD1854
Series
8
8.1
8.2
8.3
8.4
COMMAND DESCRIPTIONS
Set Lower Column Address [00~0F]
This command specifies the lower nibble of the 7-bit column address of the display data RAM.
The column address will be incremented by each data access after it is pre-set by the MCU and
returning to 0 once overflow (>127).
Set Higher Column Address [10~17]
This command specifies the higher nibble of the 7-bit column address of the display data RAM.
The column address will be incremented by each data access after it is pre-set by the MCU and
returning to 0 once overflow (>127).
Set Master/Slave Mode [18~19]
This command is used in Cascade function, programming the driver into slave mode. The Osc
clock and M clock (frame) will be received externally to synchronize the COM/SEG waveform.
Set Internal Regulator Resistors Ratio [20~27]
This command is to enable any one of the eight internal resistor (IRS) settings for different
regulator gains when using internal regulator resistor network. The Contrast Control Voltage
Range curves is referred to the following formula:
V
V
out
con
Rev 1.0
08/2002
 
1
1
R
63
R
210
2
1
 
*
V
con
*
V
ref
,
where
Vref
2
1 .
V
SOLOMON
26

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