54F109DM NSC [National Semiconductor], 54F109DM Datasheet - Page 2

• Manufacturer Part Number: 54F109DM
• Description: Dual JK Positive Edge-Triggered Flip-Flop
• Manufacturer: NSC [National Semiconductor]

PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv
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Connection Diagrams
Unit Loading/Fan Out
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
N
X = Immaterial
Q
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
See Section 0 for U.L. definitions
J
CP
C
S
Q
0
1
D1
D1
S
1
= LOW-to-HIGH Transition
(Q
, J
H
H
H
H
H
H
L
L
Pin Names
, Q
1
D
, S
0
, C
, CP
2
) = Before LOW-to-HIGH Transition of Clock
, K
2
D2
D2
, Q
1
2
, K
1
C
, Q
H
H
H
H
H
H
L
L
D
2
2
Inputs
for DIP, SOIC and Flatpak
CP
N
N
N
N
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
X
X
X
L
Pin Assignment
X
X
X
X
J
h
h
l
l
DS009471-1
K
X
X
X
X
h
h
Description
l
l
Q
Q
Q
H
H
H
L
L
Outputs
0
0
Toggle
Q
Q
Q
H
H
H
L
L
0
0
2
HIGH/LOW
50/33.3
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
U.L.
Proof
54F/74F
Output I
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.8 mA
20 µA/−1.8 mA
−1 mA/20 mA
Pin Assignment
Input I
for LCC
IH
OH
/I
/I
IL
OL
DS009471-2
2
DSXXX