LRI64-A6S2U STMICROELECTRONICS [STMicroelectronics], LRI64-A6S2U Datasheet - Page 16

• Manufacturer Part Number: LRI64-A6S2U
• Description: Memory tag IC at 13.56 MHz, with 64-bit unique ID and WORM user area, ISO 15693 and ISO 18000-3 Mode 1 compliant
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LRI64 to VCD frames
9
9.1
9.2
Figure 11. Response SOF, using high data rate and one subcarrier
Figure 12. Response EOF, using high data rate and one subcarrier
16/52
LRI64 to VCD frames
Response frames are delimited by a start of frame (SOF) and an end of frame (EOF) and
are implemented using a code violation mechanism. The LRI64 supports these in the one
subcarrier mode, at the fast data rate, only.
The VCD is ready to receive a response frame from the LRI64 before 320.9µs (t
having sent a command frame.
LRI64 SOF
SOF comprises three parts: (see
●
●
●
LRI64 EOF
EOF comprises three parts: (see
●
●
●
37.76 µs
an unmodulated period of 56.64 µs,
24 pulses of 423.75 kHz (f
a logic 1 which starts with an unmodulated period of 18.88 µs followed by 8 pulses of
423.75 kHz.
a logic 0 which starts with 8 pulses of 423.75 kHz followed by an unmodulated period of
18.88 µs.
24 pulses of 423.75 kHz (f
an unmodulated time of 56.64 µs.
113.28 µs
c
C
/32),
/32),
Figure
Figure
11)
12)
113.28 µs
37.76 µs
1
) after
AI06675B
AI06671B
LRI64