M368L2923BTM-CCC SAMSUNG [Samsung semiconductor], M368L2923BTM-CCC Datasheet - Page 4

• Manufacturer Part Number: M368L2923BTM-CCC
• Description: DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II
• Manufacturer: SAMSUNG [Samsung semiconductor]

1.0 Ordering Information
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
2.0 Operating Frequencies
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
• SSTL_2 Interface
• 66pin TSOP II
256MB, 512MB, 1GB Unbuffered DIMM
M368L3324BT(U)M-C(L)CC/B3
M381L6523BT(U)M-C(L)CC/B3
M381L2923BT(U)M-C(L)CC/B3
M368L6523BT(U)M-C(L)CC
M368L2923BT(U)M-C(L)CC
M368L6523BT(U)N-C(L)B3
M368L2923BT(U)N-C(L)B3
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part Number
(Leaded & Pb-Free(RoHS compliant))
184Pin Unbuffered DIMM based on 512Mb B-die (x8, x16)
Density
256MB
512MB
512MB
1GB
1GB
CC(DDR400@CL=3)
package
166MHz
200MHz
3-3-3
-
Organization
128M x 64
128M x 72
32M x 64
64M x 64
64M x 72
32Mx16 (K4H511638B) * 4EA
64Mx8 (K4H510838B) * 8EA
64Mx8 (K4H510838B) * 9EA
64Mx8 (K4H510838B) * 16EA
64Mx8 (K4H510838B) * 18EA
Component Composition
B3(DDR333@CL=2.5)
Rev. 1.1 June 2005
133MHz
166MHz
2.5-3-3
-
DDR SDRAM
1,250mil
1,250mil
1,250mil
1,250mil
1,250mil
Height