EDI8L24129V10BC WEDC [White Electronic Designs Corporation], EDI8L24129V10BC Datasheet

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EDI8L24129V10BC

Manufacturer Part Number
EDI8L24129V10BC
Description
128Kx24 SRAM 3.3 Volt
Manufacturer
WEDC [White Electronic Designs Corporation]
Datasheet
128Kx24 SRAM 3.3 Volt
FEATURES
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
March 2005
Rev. 5
M
A
B
C
D
E
G
H
K
N
O
P
Q
128Kx24 bit CMOS Static
Random Access Memory Array
• Fast Access Times: 10, 12, and 15ns
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
Surface Mount Package
• 119 Lead BGA (JEDEC MO-163), No. 391
• Small Footprint, 14mm x 22mm
• Multiple Ground Pins for Maximum
Noise Immunity
Single +3.3V (±5%) Supply Operation
DSP Memory Solution
Motorola DSP5630xTM
Analog Devices SHARCTM
F
J
L
I
I/012
I/013
I/014
I/015
I/016
I/017
I/018
I/019
I/020
I/021
I/022
I/023
NC
NC
NC
NC
NC
1
PIN CONFIGURATION
GND
GND
GND
GND
GND
A13
V
V
V
V
V
V
AO
NC
NC
A5
A9
White Electronic Designs
2
CC
CC
CC
CC
CC
CC
GND
GND
GND
GND
GND
GND
A10
A14
V
V
V
V
V
NC
NC
A1
A6
3
CC
CC
CC
CC
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
W#
G#
A2
E#
4
GND
VCC
GND
GND
GND
GND
GND
A15
V
V
V
V
A11
NC
NC
A3
A7
5
CC
CC
CC
CC
GND
GND
GND
GND
GND
V
V
V
V
V
V
A12
A16
NC
NC
A4
A8
6
CC
CC
CC
CC
CC
CC
I/010
I/011
I/00
I/01
I/02
I/03
I/04
I/05
I/06
I/07
I/08
I/09
NC
NC
NC
NC
NC
7
1
DESCRIPTION
The EDI8L24129VxxBC is a 3.3V, three megabit SRAM
constructed with three 128Kx8 die mounted on a multi-
layer laminate substrate. With 10 to 15ns access times,
x24 width and a 3.3V operating voltage, the EDI8L24129V
is ideal for creating a single chip memory solution for the
Motorola DSP5630x (Figure 3) or a two chip solution for
the Analog Devices SHARCTM DSP (Figure 4).
The single or dual chip memory solutions offer improved
system performance by reducing the length of board traces
and the number of board connections compared to using
multiple monolithic devices. For example, the capacitance
load on the data lines for the BGA package is 58% less
than a monolithic SOJ solution.
The JEDEC Standard 119 lead BGA provides a 44% space
savings over using 128Kx8, 300mil wide SOJs and the BGA
package has a maximum height of 100 mils compared to
148 mils for the SOJ packages. The BGA package also
allows the use of the same manufacturing and inspection
techniques as the Motorola DSP, which is also in a BGA
package.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
DQØ-DQ23
AØ-A16
GND
V
W#
NC
E#
G#
CC
PIN NAMES
Address Inputs
Chip Enable
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (3.3V±5%)
Ground
No Connection
EDI8L24129V

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